Colbhaidh
Full Member level 6
Do you mean from a fab process point of view, or a customer to a foundry?
Pin holes in the gate oxide can arise from several sources:
1: Porous polysilicon gate layer on top of the gate oxide. This causes pinholes in the polysilicon, which is cleaned using a wet etchant that will etch oxide prior to poly oxidation. If the poly is porous, the etchant gets through the poly and etches the gate oxide-which is not supposed to happen. Solution to this is usually to reduce the deposition temperature of the poly deposition process (closer to amorphous poly). If the fab does not know if this is happening, there are some simple (destructive) analysis techniques to check for this.
2: Poor or contaminated pre-gate oxidation clean. This clean is the most critical clean in cmos processing, so it has to be perfect. Any contminants may cause issues with the oxide, pinholes being one of them. The fab will typically include test structures on every wafer which are large area capacitors. At the end of e wafer processing, these capacitors are stressed until to break and a defect density number is calculated in defects/cm2. If wafers fail a set criteria, they are scrapped. Now because an sram is so dense, sometimes the criteria for scrap may not catch the defects required to ensure a sram virgin yield (un repaired yield). If you are a customer to a foundry, ask to see the pass/fail criteria for gate oxide defectivity AND ask to see the results for all wafers you buy from them.
3: Pinholes can be caused by electrical over stress on esd events. The are usually characterised by damage to the silicon under the pinhole (melt damage). So these are easier to see by SEM or TEM of the pinhole.
4: The clean used pprior to gate oxidation uses hydrogen peroxide. H2O2 is difficult to remove metallic contaminats (Fe, Al). For dense srams, Al contamination can cause stuck bits especially at lower temperatures even at contamination levels of 1E11. Hydrogen peroxide is suplied to the fab in plastic containers. As or if they are stored over long periods of time, metals are leached out of the plastic, into the peroxide. To check for this, fabs will include a test called J-ramp or Qbd. Both measure the ability of the oxide to withstand charge injected into the oxide. As charge is forced into the oxide under stress conditions, it builds up damage. After a certain amount of charge has been forced in, the oxide collapses and breaks down. The measure is Charge to Break Down (Qbd). So if you are a customer, ask to see the specified limits for this test, and the results for the wafers you buy. This is a long (and therefore costly) test so fabs do not like it. They may therefore not do it on every wafer but chise to run what is called a Wafer Level Reliability Test run (WLR) which is run routinely but not with a customer run. Again, if a customer, ask to see the results. If they do not have them or do not run these tests then ask them why!!
Pin holes in the gate oxide can arise from several sources:
1: Porous polysilicon gate layer on top of the gate oxide. This causes pinholes in the polysilicon, which is cleaned using a wet etchant that will etch oxide prior to poly oxidation. If the poly is porous, the etchant gets through the poly and etches the gate oxide-which is not supposed to happen. Solution to this is usually to reduce the deposition temperature of the poly deposition process (closer to amorphous poly). If the fab does not know if this is happening, there are some simple (destructive) analysis techniques to check for this.
2: Poor or contaminated pre-gate oxidation clean. This clean is the most critical clean in cmos processing, so it has to be perfect. Any contminants may cause issues with the oxide, pinholes being one of them. The fab will typically include test structures on every wafer which are large area capacitors. At the end of e wafer processing, these capacitors are stressed until to break and a defect density number is calculated in defects/cm2. If wafers fail a set criteria, they are scrapped. Now because an sram is so dense, sometimes the criteria for scrap may not catch the defects required to ensure a sram virgin yield (un repaired yield). If you are a customer to a foundry, ask to see the pass/fail criteria for gate oxide defectivity AND ask to see the results for all wafers you buy from them.
3: Pinholes can be caused by electrical over stress on esd events. The are usually characterised by damage to the silicon under the pinhole (melt damage). So these are easier to see by SEM or TEM of the pinhole.
4: The clean used pprior to gate oxidation uses hydrogen peroxide. H2O2 is difficult to remove metallic contaminats (Fe, Al). For dense srams, Al contamination can cause stuck bits especially at lower temperatures even at contamination levels of 1E11. Hydrogen peroxide is suplied to the fab in plastic containers. As or if they are stored over long periods of time, metals are leached out of the plastic, into the peroxide. To check for this, fabs will include a test called J-ramp or Qbd. Both measure the ability of the oxide to withstand charge injected into the oxide. As charge is forced into the oxide under stress conditions, it builds up damage. After a certain amount of charge has been forced in, the oxide collapses and breaks down. The measure is Charge to Break Down (Qbd). So if you are a customer, ask to see the specified limits for this test, and the results for the wafers you buy. This is a long (and therefore costly) test so fabs do not like it. They may therefore not do it on every wafer but chise to run what is called a Wafer Level Reliability Test run (WLR) which is run routinely but not with a customer run. Again, if a customer, ask to see the results. If they do not have them or do not run these tests then ask them why!!
