VHDL : error with code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity xnor_gate is
port (in1 : in std_logic;
      in2 : in std_logic;
		out1 : out std_logic);
end xnor_gate ;

architecture x of xnor_gate is 
begin
out1<=in1 xnor in2;
end x;

entity and_gate is
port (ind1 : in std_logic ;
      ind2 : in std_logic;
		ind3 : in std_logic;
      ind4 : in std_logic;
		out1 : out std_logic);		
end entity;

architecture xx of and_gate is 
begin
out1<=ind1 and ind2 and ind3 and ind4;
end xx;

entity components_trial is
    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           op : out  STD_LOGIC);
end components_trial;


architecture Behavioral of components_trial is

component xnor_gate is
port (in1 : in std_logic;
      in2 : in std_logic;
		out1 : out std_logic);
end component;

component and_gate is
port (ind1 : in std_logic;
      ind2 : in std_logic;
		ind3 : in std_logic;
      ind4 : in std_logic;
		out1 : out std_logic);		
end component;

signal w,x,y,z : std_logic;

begin

u1:xnor_gate 
port map ( in1=>a(0) ,
           in2=>b(0) ,
			  out1=> w);
			  
u2:xnor_gate 
port map ( in1=>a(1) ,
           in2=>b(1) ,
			  out1=> x);
u3:xnor_gate 
port map ( in1=>a(2) ,
           in2=>b(2) ,
			  out1=> y);
u4:xnor_gate 
port map ( in1=>a(3) ,
           in2=>b(3) ,
			  out1=> z);
u5:and_gate 
port map ( ind1=>w ,
           ind2=>x ,
			  ind3=>y,
           ind4=>z ,

			  out1=> op);
			  
			  



end Behavioral;