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yes it is possible in the case of mixed signal modelling.by using either Averiog or AMSvhdl language but for these things we need simulators which supports analog and mixed signal hdl.we cant run this using either xilinx or quartus ise..
FPGA usually have internal pullups that can be enabled from the IDE properties for each pin, I think it can be done through the code too, is this what you mean?
The altera coding guide makes no mention of infering pull-ups from code. So you will have to do it the "normal" way. Create settings that make the default whatever and the individual pin exceptions osmething else.
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