Asynchronous CPLD design

Hello,

Is it possible to design a CPLD without a clock source ?

Yes. You select for each cell if the output should have a clocked register or not.

Of course. You can implement combinational logic, latches and FFs clocked from the data inputs.

Would you recommand it?
I understand it's done to save energy - right ?

The decision depends mostly on the design purpose and operation conditions. Energy and resource savings can be achieved in some cases.

shaiko said:

Would you recommand it?
I understand it's done to save energy - right ?

Click to expand...

Maybe we have a misunderstanding here. Do you mean asynchronous state machines? Combinatorial logic with feedback?
It is possible but you will spend much more time with design and verification since the tools will not help you much.
It is difficult for the tools to see if you create something useful or an oscillator.

You can do it in any technology, CPLD, FPGA, ASIC.

shaiko said:

Would you recommand it?
I understand it's done to save energy - right ?

Click to expand...

I don't know about in a CPLD, but I can say that in an FPGA, with a reference design provided by a proponent of such things who was trying to patent some ideas in that area, the gated clock approach lost out badly to the synchronous approach. Used more power, ran more slowly...totally contrary to his claim. This was targetting Cyclone III/IV type devices. I suspect that the culprit on the power side is that the global clock resources in the FPGA have much lower capacitance and therefore consume much less power when switching that it came out ahead of the 'only clock when you need to' approach.

CPLDs on the other hand are sometimes designed to be extremely power stingy and probably can benefit from an asynchronous approach if you need to be as thrifty as possible on the power front. Don't expect it to be automatic is my only caution.

Kevin Jennings

std_match,

The project I'm working on, involves a PCB with a small CPLD that has no clock.
Apparently, it has been done to save power.
The purpose of the device is to "wakeup" a DSP that's also on the board.

No FSM is required - but I would have to use storage elements (latches...) and simple combinatorial logic.

I forgot to mention, that the ability to save power is primarly a matter of the involved CPLD family. In contrast to FPGA, most classical CPLD aren't "zero power", means up to several MHz clock statical power consumption (quiescent current) is higher than dynamical (clock related) power demand. With these types, power saving by asynchronous design techniques would be pointless.

On the other hand, classical CPLD macrocell logic arrays have less tendency to create glitches and also implement a very simple timing scheme, so it's much easier to create reliable asynchronous circuits than with FPGA, at least in manual design. Missing support of asynchronous circuit timing analysis also affects HDL CPLD design.

In my case, I think that most of the power savings will be from the very absence of a clock oscillator.
The device itself is a very low power ACTEL IGLOO NANO.

Yes, Actel IGL00 is a FPGA (involving SRAM based logic cells) family with built-in configuration flash. Not a classical CPLD.

Aren't the IGLOO's logic cells flash based??

Yes, you are right. IGLOO has flash cells inside the logic array. But unlike classical CPLD it's pure a pure CMOS design with very low cuiescent current.