memory synthesis vhdl code

Hi all;

I found a memory code,but I think it is not synthesis because it use file command. Is it the code below is synthesis? If not, how to make it synthesis? Thank you

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

use std.textio.all;
use ieee.std_logic_textio.all;

entity Memory is
generic
(
WIDTH : integer := 512;
HEIGHT : integer := 512; -- IMAGE_MEMORY_SIZE
ADDR_BUS_WIDTH : integer := 19;
INPUT_FILENAME : string := "TestData.txt";
OUTPUT_FILENAME : string := "DWTResult.txt"
);
port
(
cs : in std_logic;
rd : in std_logic;
wr : in std_logic;
dump : in std_logic;
addr : in std_logic_vector(ADDR_BUS_WIDTH - 1 downto 0);
datain : in std_logic_vector(7 downto 0);
dataout : out std_logic_vector(7 downto 0)
);
end Memory;

architecture Behavioral of Memory is

type memory_type is array(0 to WIDTH*HEIGHT - 1) of std_logic_vector(7 downto 0);
signal mem : memory_type; -- instance of memory: image data

procedure FillMemory(signal omem: out memory_type; file_name: string) is
file ifile : TEXT is in file_name;
variable l_in : LINE;
variable dt : std_logic_vector(7 downto 0);
begin
for ty in 0 to HEIGHT/2 - 1 loop
readline(ifile, l_in);
for tx in 0 to WIDTH - 1 loop
hread(l_in, dt);
omem(tx + WIDTH*ty) <= dt;
end loop;
end loop;
end;

procedure DumpMemory(imem: in memory_type; file_name: string; lower_addr_half: boolean) is
file ofile : TEXT is out file_name;
variable l_out : LINE;
variable dt : std_logic_vector(7 downto 0);
begin
if lower_addr_half then
for ty in 0 to HEIGHT/2 - 1 loop
for tx in 0 to WIDTH - 1 loop
dt := imem(tx + WIDTH*ty);
hwrite(l_out, dt);
write(l_out, ' ');
end loop;
writeline(ofile, l_out);
end loop;
else
for ty in HEIGHT/2 to HEIGHT - 1 loop
for tx in 0 to WIDTH - 1 loop
dt := imem(tx + WIDTH*ty);
hwrite(l_out, dt);
write(l_out, ' ');
end loop;
writeline(ofile, l_out);
end loop;
end if;
end;

begin

process(cs, rd, wr, dump, addr, datain)
variable mem_init : boolean := false;
variable reorder_mem : memory_type;
begin

if (not mem_init) then
mem_init := true;
if INPUT_FILENAME'length > 0 then
FillMemory(mem,INPUT_FILENAME);
end if;
end if;

if (dump'event and dump = '1') then
if OUTPUT_FILENAME'length > 0 then
DumpMemory(mem,OUTPUT_FILENAME,TRUE);
DumpMemory(mem,"DWT_VERSD.txt",FALSE);
end if;
end if;

if (cs = '1') then
if (wr = '1') then
mem(CONV_INTEGER(UNSIGNED(addr))) <= datain;
elsif (rd = '1') then
dataout <= mem(CONV_INTEGER(UNSIGNED(addr)));
else
dataout <= (others => 'Z');
end if;
end if;
end process;
end Behavioral;

The code is obviously intended as simulation model. I'm not aware of a design compiler supporting textio file commands for memeory initialization, they are using proprietary data formats, e.g. hex files with memory IP. Verilog initialization files are e.g. supported by Altera Quartus.

Apart from the textio problem, the code is describing an asynchronous RAM and can't be synthesized to internal memory blocks of popular FPGAs, only to a bank of latches.

FvM said:

The code is obviously intended as simulation model. I'm not aware of a design compiler supporting textio file commands for memeory initialization, they are using proprietary data formats, e.g. hex files with memory IP. Verilog initialization files are e.g. supported by Altera Quartus.

Apart from the textio problem, the code is describing an asynchronous RAM and can't be synthesized to internal memory blocks of popular FPGAs, only to a bank of latches.

Click to expand...

Hi FvM,

Actually I'm trying to save data in sdram something like:
m(n+0) m(n+2)
m(n+1) m(n+3) where n=0 to 508

How can I do that? I don't know how to start write the vhdl code..can you give me the starting idea..really appreciates your helps.Thank you

fanwel said:

Hi FvM,

Actually I'm trying to save data in sdram something like:
m(n+0) m(n+2)
m(n+1) m(n+3) where n=0 to 508

How can I do that? I don't know how to start write the vhdl code..can you give me the starting idea..really appreciates your helps.Thank you

Click to expand...

Assuming that you have inputs like the following...
Then you can define a couple of data types and a signal to represent the memory...
Then you can write the following process which will infer use of memory that is internal to the FPGA

That should get you started and well on your way.

Kevin Jennings

Hi Kevin Jennings,

The code you give is a memory code right? My idea is to use the sdram controller using sopc builder to store the 2x2 data until end.
Know, I need to design the 2x2 structure from 512x512 before send this values to the sdram. I have no idea to write the code for the 2x2 structure..can you give some hint code? Thanks for reply

I don't understand how your initial post and the question title "memory synthesis vhdl code" is related to SDRAM. An SDRAM controller has a particular interface to read and write data. You need to refer to the description of the respective IP core.

Generally any RAM has a linear structure of m memory locations x n bits. Structures are only a matter of mapping user defined entities to linear addresses. Multi word entities have to be read and written sequentially, e.g. one word per clock cycle.

In a sopc builder design, the memory operation are usually performed by a soft processor, programmed in C.

Hi FvM,

I think I have misunderstood about memory in fpga. I have study on SDRAM from altera documents and I have some questions:

1) Why SDRAM is not related with "memory synthesis vhdl code"?.
2) I try to write/read data to/from SDRAM chip in fpga. I will control the SDRAM using Megafunction Wizard in quartus. Can I do like that?
3) Is it sopc builder MUST perform the memory operation in C? Can't use vhdl?

I'm sorry, maybe I ask a simple questions. But I need certainty about my knowledge. Really appreciate your helps..thank you

Using a SDRAM controller core is different form memory synthesis.

You can use a SDRAM controller without soft processor, just with a native VHDL design. But what's the point of using SOPC builder then?

FvM said:

Using a SDRAM controller core is different form memory synthesis.

You can use a SDRAM controller without soft processor, just with a native VHDL design. But what's the point of using SOPC builder then?

Click to expand...

Hi FvM,

I'm new to SOPC builder. What I understand is SOPC builder can be used as a SDRAM controller (short way without write the controller code by self). We just need to setup the parameter and signals needed.

What do you mean by "You can use a SDRAM controller without soft processor, just with a native VHDL design"? And how about my second point from the previous post, is it possible? Thanks for reply..

If you refer to DDR SDRAM, there's an Altera Megafunction but not for SDR SDRAM.

Hi all;

I has study on simple sram controller. Its successfully compile in quartus and simulate it in Modelsim.
What I weird is the value of led is "0000". It should be "0101" I think. I attach the code with testbech code and the waveform in modelsim.
Can anyone check it for me? And what my mistake actually? Thank you..