shaiko
Advanced Member level 5
Hello,
Please review the following code for an asynchronous assert synchronous deassert reset circuit.
"rst_i" is an external signal to the IC and "global_rst_o" is the global reset signal intended for destribution as an asynchronous reset for all the registers in the design.
tell me what you thing about it.
Please review the following code for an asynchronous assert synchronous deassert reset circuit.
"rst_i" is an external signal to the IC and "global_rst_o" is the global reset signal intended for destribution as an asynchronous reset for all the registers in the design.
tell me what you thing about it.
entity rst_generator is
port
(
clk_i, -- global clock input
rst_i: in std_logic; -- external reset input
global_rst_o: out std_logic -- global reset output
);
end entity rst_generator;
architecture rtl_rst_generator of rst_generator is
signal reg_rst_inp: std_logic;
begin
process (clk_i,rst_i) is
begin
if rst_i = '1' then
reg_rst_inp <= '1';
global_rst_o <= '1';
elsif rising_edge(clk_i) then
reg_rst_inp <= '0';
global_rst_o <= reg_rst_inp;
end if;
end process;
end architecture rtl_rst_generator;