Error when connect Character & Graphics LCD

I have problems when connect two LCD: Character & Graphics together. Some comon signals don't allow to connect : write enable pin, data/command select pin. How do I correct this error ? I use Cyclone II dev kit
Thanks.

ngtrung99 said:

I have problems when connect two LCD: Character & Graphics together. Some comon signals don't allow to connect : write enable pin, data/command select pin. How do I correct this error ? I use Cyclone II dev kit
Thanks.

Click to expand...

How do you correct that error? Simple. Fix the thing with the color. You know, the one with that particular characteristic. It causes things, hence you change that. Glad I could help!


On a slightly less unhelpful note ... please re-read your post. Now imagine you are someone who cannot read minds. How do you expect people to help you based on that information? Please be a bit more specific.

I'm done on the system board kit dev cyclone iii. My system includes components such as: cpu,jtag,mem, character LCD, PIOs role graphic LCD.

My verilog program as follows:

module bt4 (clkin_50, cpu_resetn, lcd_data, lcd_csn, lcd_d_cn, lcd_e_rdn, lcd_rstn, lcd_wen, lcd_en);

input clkin_50;
input cpu_resetn;
inout [7:0]lcd_data;
output lcd_csn;
output lcd_d_cn;
output lcd_e_rdn;
output lcd_rstn;
output lcd_wen;
output lcd_en;

nios_sys DUT (
// 1) global signals:
.clk_0(clkin_50),
.reset_n(cpu_resetn),

// the_GLCD_CSN
.out_port_from_the_GLCD_CSN(lcd_csn),

// the_GLCD_DATA
.in_port_to_the_GLCD_DATA(lcd_data[7:0]),
.out_port_from_the_GLCD_DATA(lcd_data[7:0]),

// the_GLCD_D_CN
.out_port_from_the_GLCD_D_CN(lcd_d_cn),

// the_GLCD_E_RDN
.out_port_from_the_GLCD_E_RDN(lcd_e_rdn),

// the_GLCD_RSTN
.out_port_from_the_GLCD_RSTN(lcd_rstn),

// the_GLCD_WEN
.out_port_from_the_GLCD_WEN(lcd_wen),


// the_lcd_0
.LCD_E_from_the_lcd_0(lcd_en),
.LCD_RS_from_the_lcd_0(lcd_d_cn),
.LCD_RW_from_the_lcd_0(lcd_wen),
.LCD_data_to_and_from_the_lcd_0(lcd_data[7:0])
)
;
endmodule


But when compiling errors because 2 signals lcd_wen and lcd_d_cn are common signals.

Have you considered giving us the complete, unedited errors?

Could you include the error?

yes. i don't know how to correct this error.
This error is fanout because the signals i map twice lcd_wen and lcd_d_cn

ROFL! Thanks for repeating that. I failed reading it the first time.

The hint is: please copy/paste the entire error from the synthesis report. That way we don't have to guess.

yes. thanks. Help me please!!

Good thing I took my patience inducing vitamins today...

You run your synthesis software, yes? And it gives you a nice error message, right? COPY that error, and PASTE it in your post please. Or take a screenshot, that works as well if the copy/paste function is not working where you live.

my error is: """Net "lcd_d_cn", which fans out to "lcd_d_cn", cannot assign more than one value"""". The same error with lcd_wen.

I assume it's because you've got these lines:

.out_port_from_the_GLCD_D_CN(lcd_d_cn),
.out_port_from_the_GLCD_WEN(lcd_wen),

.LCD_RS_from_the_lcd_0(lcd_d_cn),
.LCD_RW_from_the_lcd_0(lcd_wen),

and all four of them are drivers.

I'm not at all familiar with Nios, but is there any particular reason why you have both GLCD_ and LCD_ ports?

Well, you are trying to assign something to the "lcd_d_cn" twice. That's not going to work.

Assignment 1:


Assignment 2:

You have one wire, and then are connecting two drivers to it. The tools don't know which one you really meant, so you get an error.

---------- Post added at 15:32 ---------- Previous post was at 15:31 ----------

Stop typing faster. GNNNN.


;-)

my project must use both GLCD and character LCD. But those signals are common. I don't know how to correct it. Can I add in my SOPC a tristate to correct them ? How it design ?

A tri-state won't work.

If the two LCDs really do have their wen and d_cn ports tied together (seems like a silly design decision), maybe you could just OR the two signals together before outputting them.

You might have to study what the manual says about this. I had a quick look but wasn't willing to download a 364 MB executable just to look at the schematic diagram.