Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

ADC 16 channels input/output

Status
Not open for further replies.
I

icd

Junior Member level 3
Joined
Jan 25, 2012
Messages
25
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,506
Hi,
i am working on a data acquisition system and i need to convert the analog data that is coming from the photo diode to digital using large number of ADCs. i am usnig 8-Channel ADC ( 8 inputs and 8 outputs). the ADC processes 18 samples per pulse each sample 12 bits. my question is there any ADC with 16-channels ( 16 inputs - 16 outputs), with high performance can i use to decrease the number of ADCs that are used? i found 16-channel inputs and 1 channel output (parallel input serial output).

thanks
 

First did you qualify the ADC for your sampling requirements?. B'Coz More no of channels less sampling frequency. If you are still looking for 16-channel, then it will be like 16x down sampling when compared to 1 channel ADC.
 
  • Like
Reactions: icd

    I

    icd

    Points: 2
    Helpful Answer Positive Rating
thanks all for ur help :)
to be honest im not familier with ADCs. anyhow i saw the attached file of tbetar and im not sure if it has 16-channel output. maybe my understanding is wrong.
pls see the attached for more details im using this ADC and im looking for the same one with 16-channel I/O instead of 8-channel I/O. : Untitled.jpg
 

since there is no other reply, let's change the question ;). is there any type of fpga that has an internal ADC with the same specification in the attached file above?
 
Last edited:

Not that I know. Some of the Actel parts have multiple ADC channels, though it's not clear how many channels, and they are probably not 1 MSPS at 12-bit.

In general, an external ADC will have superior performance.

The AD7490 has sixteen channels, but it does not sample them simultaneously and the total throughput is up to 1 MSPS. Unless you have to build an incredibly tiny device, I wouldn't worry too much about having 2-4 ADCs if that's the easiest option. Alternatively, you could use a CCD or CMOS image sensor instead of discrete photodiodes.

Any reason why you don't want serial output? As long as the ADC supports simultaneous sampling (if this is what you need), you can easily separate the samples.
 
  • Like
Reactions: icd

    I

    icd

    Points: 2
    Helpful Answer Positive Rating
The thing is first he should be aware of ADC sampling requirements. What's the application are you trying to do with ADC?. That's why I asked your requirements. Or tell me the application, will try to find out the requirements.

---------- Post added at 12:29 ---------- Previous post was at 12:28 ----------

Yes, ADC's internal in a mixed signal FPGA from Lattice are low speed only to be used for some sensory operations....
 

Can't see any attachments.. but can you describe exactly what you're struggling with?
 

OK, pls see the attachment and lemme know if u need more info. it's a data acquisition system and im struggling with the ADC part since im not familiar with ADCs.
i need to convert the analog data to digital using the ADC.Untitled2.jpgUntitled.jpg
 

Are you planning to implement that design as-is? If so, what exactly are you having trouble with? What have you done so far?
 

okay, first calculate what's your input power in terms of dB as well as the input analog signal frequency. These two things are really so important that you must be aware when you are dealing with ADC's. Improper input power to ADC input can result in offset errors giving totally bad digits per voltage. Then comes frequency part which if is out of ADC's sampling range, you will lose more information from your signal when converting it to digital. These two factors majorly help you in deciding ADC. Tell us your data-acquisition sources.
 
  • Like
Reactions: icd

    I

    icd

    Points: 2
    Helpful Answer Positive Rating
Hi again,

Thanks for all the replays. Appreciate it!

Im using ADS5281 the one in the attachment below. it has 8-input channels that will accept 8 analog values which are coming from number of (4*4 photodetectors=16). so i need 2 ADCs for each photodetector as u see in the second pic so i need larg number of ADCs. the output of each analoge value will be 12-bit digital.
im looking for 16-channel input ADC that will accept the 16 analog values that are coming from 4*4 photodetector. and 16 channel output 12-bit for each analog value 50MSPS. i.e the output of each analog value is 12-bit serial. but the number of channels is 16.
untitled.png
untitled2.png
 
Last edited:

I'm not sure - I haven't used one. Either use more ADCs or use analogue multiplexers so that you can scan the whole photodetector array with a lower number of fast ADCs. Alternatively, consider using some sort of camera module, which does all of this for you at resolutions higher than 256x256.
 

icd said:
Hi again,

Thanks for all the replays. Appreciate it!

Im using ADS5281 the one in the attachment below. it has 8-input channels that will accept 8 analog values which are coming from number of (4*4 photodetectors=16). so i need 2 ADCs for each photodetector as u see in the second pic so i need larg number of ADCs. the output of each analoge value will be 12-bit digital.
im looking for 16-channel input ADC that will accept the 16 analog values that are coming from 4*4 photodetector. and 16 channel output 12-bit for each analog value 50MSPS. i.e the output of each analog value is 12-bit serial. but the number of channels is 16.
View attachment 69297
View attachment 69298
Click to expand...

16-channels in single ADC and that too with 50MSps?.....I have never heard this before.

Also, you said the output clk is 36MHz, rite?. The datasheet shows it is serial read with clock as you said 36M. Now for a 12-bit of one channel, 36MHz\12-bit = 3MSps which will be the actual output rate for your FPGA lvl1. Because of this, the output rate determines the maximum possible sample rate which will restrict your ADC's sample rate to 3MHz and not any better.

The photo-array detector which you mentioned, can you check it's output frequency?.
 
  • Like
Reactions: icd

    I

    icd

    Points: 2
    Helpful Answer Positive Rating
i really appreciate your patience guys :). my professor is making my life miserable. is it possible to make this ADC in Verilog-A but in structure model not behavior. any help is appreciated.
 

glad u r here again bro.
now as we r making this system schematic, i need to do the ADC with the same requirements using Verilog-A, but the problem i need to do it in structural models not behavioral. i might do it in behavioral models but structural is a little bit hard since im not familiar with Verilog-A.
 

Verilog-A ???
Oops.... :-(
Sorry bro, No idea, me either...Maybe wait for someone to help you in this case
 

Hi dear icd*
you can make it with op-amp . for more voltage. but it is a little big!!??
but its very good.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top