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Port Mapping with process

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masoud.malekzadeh

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Hi , I've stored data from text file to ROM and i want to use Xilinx IP core to add two lines of Rom but it is not working ....

Here is my code ....





library IEEE;
use ieee.std_logic_textio.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use std.textio.all;


entity ROM is

port (
x_out: out std_logic_vector(31 downto 0 );
clk: in std_logic
);

end ROM;

architecture Behavioral of ROM is

type ram_type is array (9 downto 0 ) of std_logic_vector(31 downto 0 );
signal ram :ram_type;

signal w:std_logic_vector(31 downto 0);
signal z:std_logic_vector(31 downto 0);
signal t:std_logic_vector(31 downto 0);


component adder
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
clk: in std_logic;
result: out std_logic_vector(31 downto 0));
end component;



begin



process(clk)

FILE infile : TEXT is in "in_code.txt";
FILE outfile : TEXT IS OUT "out_code.txt";
VARIABLE out_line: LINE;
variable my_line : line;
variable int: std_logic_vector(31 downto 0 ) ;
variable i :integer range 9 downto 0 :=0;

begin

if(clk' event and clk='1') then

readline(infile,my_line);

read (my_line,int);
ram(i)<=int;
i:=i+1;
write(out_line,int);
writeline(outfile,out_line );


end if ;




end process;

g1:adder port map (a => ram(2),b => ram(4),clk => clk,result =>x_out);

end Behavioral;
 

please explain what is not working.
Are you trying to compile this code in ISE, because you cannot compile this for an FPGA - you can only simulate it. textio is not suitable for FPGAs (only suitable for simulation).
 

the hole code is working well i stored my data in rom but i the Port map is not working that is the result is zero ....
 

masoud.malekzadeh said:
the hole code is working well i stored my data in rom but i the Port map is not working that is the result is zero ....
Click to expand...

You leave a lot of information out which makes it difficult to interpret. Here are some points of confusion:
- While you did post code, you didn't post all of it, the 'adder' entity is missing. One would have to assume (and probably correctly) that adder simply adds 'a' and 'b' so this is not a big thing.
- You say the hole (sic) code is working well...but the port map is not working that the result is zero. Some obvious questions: Which code is 'working' and which part is 'not working'. What result is zero? Why do you suspect the port map? Hint: It's not the port map

So here is my guess as to what is going on:
- The output 'result' is 0...but that's because you didn't run the simulation for the 5 clock cycles that are needed to get a valid output (more on that in a bit).
- The simulation will die if you run the simulation for more than 9 clock cycles because the variable 'i' will attempt to be set to 10, but the declared range of i is '9 downto 0'.
- You're likely incrementing the variable 'i' at the wrong time in the process...the whole table is not being written out.
- For some unknown reason, you have a synchronous process for reading in the contents of your ROM table (This is the root cause of the problems you are seeing). What this means then is that address 0 gets loaded on the first clock cycle, address 1 on the second clock cycle, etc. That might be what you want, but based on the previous two errors I doubt it. What you likely need this process to be is the following:

Code: 
process
    FILE infile : TEXT is in "in_code.txt";
    FILE outfile : TEXT IS OUT "out_code.txt";
    VARIABLE out_line: LINE;
    variable my_line : line;
    variable int: std_logic_vector(31 downto 0 ) ;
begin 
    for i in 0 to 9 loop
        readline(infile,my_line);
        read (my_line,int);
        ram(i)<=int;
        write(out_line,int);
        writeline(outfile,out_line );
    end loop ;
    wait; -- Waits forever
end process;

Kevin Jennings
 
I haven't declare entity for adder because i'm using Xilinxs Ip core Generator , and thanks my problems got fixed that i changed your code instead of mine , i did not clock problem i think it was because of my process architecture .

By the way any idea why i cant use port map in loop to add 10 rows of may data ?

Thanks .
 

masoud.malekzadeh said:
I haven't declare entity for adder because i'm using Xilinxs Ip core Generator , and thanks my problems got fixed that i changed your code instead of mine , i did not clock problem i think it was because of my process architecture .

By the way any idea why i cant use port map in loop to add 10 rows of may data ?

Thanks .
Click to expand...

Again, without more details your problem is not very clear. Are you trying to use a genate loop?
 

IN the same code i want to add all the 10 rows of data by using port map

here is the code


library IEEE;
use ieee.std_logic_textio.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use std.textio.all;


entity ROM is

port (
x_out: out std_logic_vector(31 downto 0 );
clk: in std_logic

);

end ROM;

architecture Behavioral of ROM is

type ram_type is array (9 downto 0 ) of std_logic_vector(31 downto 0 );
signal ram :ram_type;

signal w:std_logic_vector(31 downto 0);
signal z:std_logic_vector(31 downto 0);
signal t: std_logic_vector(31 downto 0):="00000000000000000000000000000000";


component adder
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
clk: in std_logic;
result: out std_logic_vector(31 downto 0));
end component;



begin

process
FILE infile : TEXT is in "in_code.txt";
FILE outfile : TEXT IS OUT "out_code.txt";
VARIABLE out_line: LINE;
variable my_line : line;
variable int: std_logic_vector(31 downto 0 ) ;
begin
for i in 0 to 9 loop
readline(infile,my_line);
read (my_line,int);
ram(i)<=int;
write(out_line,int);
writeline(outfile,out_line );
end loop ;
wait; -- Waits forever
end process;


for i in 0 to 8 loop

g1:adder port map (a => ram(i),b=>t,clk => clk,result =>t);

end loop ;
x_out<=t ;
end Behavioral;



when i use for loop i get

Syntax error near "loop".
Syntax error near "for ".
 

for i in 0 to 8 loop
g1:adder port map (a => ram(i),b=>t,clk => clk,result =>t);
end loop ;

when i use for loop i get

Syntax error near "loop".
Syntax error near "for ".
Click to expand...

The reason is that a 'for' statement must be in a process, but a process cannot instantiate another entity. However, when you want to instantiate multiple instances of the same entity, you would use the 'generate' statement like this:

Code: 
GEN_ADDERS : for i in 0 to 8 generate
     g1:adder port map (a => ram(i),b=>t,clk => clk,result =>t(i));
end generate;
Notice though that the output 't' is also a vector of results. Now you can add up the elements of 't' if you'd like in a process like this:

Code: 
process(t)
  variable Sum: unsigned(31 downto 0);
begin
  for i in 0 to 8 loop
    Sum := Sum + unsigned(t(i));
  end loop;
  xout <= std_logic_vector(Sum);
end process;
Kevin Jennings
 

Thanks for your help kevin ,but my data is floating point and the adder is a pre defined floating point adder , I have the same problem for adding t(i) i should use the adder component by port map .
 

if your adder is floating point, why do you need 9 of them?
 

masoud.malekzadeh said:
Thanks for your help kevin ,but my data is floating point and the adder is a pre defined floating point adder , I have the same problem for adding t(i) i should use the adder component by port map .
Click to expand...

Then I suggest you abandon your current approach of trying to have multiple adders, instead you need one adder that works as an accumulator. The ram data then gets sequenced through the adder on successive clock cycles.

Code: 
process(clk)
begin
  if rising_edge(clk) then
    if (reset = '1') then -- Something that resets the accumulated sum to 0
      Prev_Sum <= (others => '0');  -- The accumulated sum
      i <= 0;
    elsif (i <= 8) then
      Prev_Sum <= t;  -- Save the updated sum
      i <= i + 1;
    end if;
  end if;
end process;

g1 : adder port map (a => ram(i),b=>Prev_Sum,clk => clk,result =>t);

Kevin Jennings
 

process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then -- Something that resets the accumulated sum to 0
Prev_Sum <= (others => '0'); -- The accumulated sum
i <= 0;
elsif (i <= 8) then
Prev_Sum <= t; -- Save the updated sum
i <= i + 1;
end if;
end if;
end process;

g1 : adder port map (a => ram(i),b=>Prev_Sum,clk => clk,result =>t);

For working this code i declared the sing i integer range 9 downto 0 but i get the error

Actual for formal port a is neither a static name nor a globally static expression

Dont you think that the port map just works only once !?


thanks
 

you will need to build the ram from the correct template. You cannot infer extra logic (a mux in this case) inside a port map. You will need a temporary signal to carry the value to A:

signal ram_value : std_logic_vector(7 downto 0);

ram_value <= ram(i);


g1 : adder port map (a => ram_value,b=>Prev_Sum,clk => clk,result =>t);
 

I have modified my code as you said but surprisingly Prev_Sum is always zero and t equals to w ...

library IEEE;
use ieee.std_logic_textio.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use std.textio.all;


entity ROM is

port (
x_out: inout std_logic_vector(31 downto 0 );
x_in: inout std_logic_vector(31 downto 0 );
clk: in std_logic;
reset:in std_logic
);

end ROM;

architecture Behavioral of ROM is

type ram_type is array (9 downto 0 ) of std_logic_vector(31 downto 0 );
signal ram :ram_type;

signal w:std_logic_vector(31 downto 0);

signal y:std_logic_vector(31 downto 0);
signal t:std_logic_vector(31 downto 0);
signal Prev_Sum:std_logic_vector(31 downto 0);
signal i : integer range 9 downto 0 :=0;

component adder
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
clk: in std_logic;
result: out std_logic_vector(31 downto 0));
end component;



begin

process
FILE infile : TEXT is in "in_code.txt";
FILE outfile : TEXT IS OUT "out_code.txt";
VARIABLE out_line: LINE;
variable my_line : line;
variable int: std_logic_vector(31 downto 0 ) ;
begin
for i in 0 to 9 loop
readline(infile,my_line);
read (my_line,int);
ram(i)<=int;
write(out_line,int);
writeline(outfile,out_line );
end loop ;
wait; -- Waits forever


end process;



process(clk)

begin
if rising_edge(clk) then

if (i <= 9) then
Prev_Sum <= t;
w<=ram(i);
i <= i + 1;
end if;
end if ;
end process;

g1 : adder port map (a => Prev_Sum,b=>w,clk => clk,result =>t);

end Behavioral;
 

What initializes the adder? This component has a clock so therefore I assume that 'result' is clocked, but there is no way to initialize it to anything at the start.

KJ
 

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