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It's sometimes used in the 65nm process. But I think I found the answer (at least partially): "2.5V under-drive 1.8V is a kind of device, the vcc can be 1.8V by changing gate length, no need any extra mask. So is 2.5V over-drive 3.3V. They are available in the N65 process with IO is 2.5V."
But I'm still a bit puzzled: looking at the TSMC pdk, especially nch_25 vs. nch_25od33. The only difference I see is the change in gate length: 0.28 vs 0.5 and an OD_25 ovdrv layer. Does this OD_25 do something (process-wise) to the device? Or are they basically the same devices with a different gate length? If so, why is it separately defined in the pdk/mentioned as a TSMC process option?
As near as I can make it out, this is saying you can drive the
gate to greater voltage than is allowed drain-source. This
is not unusual, most short channel FETs are limited by hot
carrier effects D-S and TDDB G-S / G-D, with the gate ox
being the more capable.
I've just never seen anybody turn that into a "feature".
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