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[SOLVED] High 'Z'ding chosen bits of a register

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shaiko

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I'm writing VHDL code for an FPGA that sits on a PCB with a design error .
The're FPGA registers that are mapped to output pins - 3 of the pins in the PCB schematics, have been accidentally shorted to a single trace...I want only one of those output pins to drive a valid logic value and the others high 'Z'.

This is the code for the output registers:
what do you think about it ?

-- memory is a 16 X 16 flipflop array
if rising edge ( clk ) then
if write_request = '1' then
if write_address = "00001111" then -- this is the register address whose 3 of his bits are shorted on the PCB
memory ( 15 ) ( 15 downto 3 ) <= internal ( 15 downto 3 ) ;
mem_out ( 15 ) ( 2 downto 1 ) <= "ZZ" ;
mem_out ( 15 ) ( 0 ) <= data ( 0 ) ;
else
mem ( to_integer ( write_address ) ) <= data ;
end if ;
end if ;
end if;
Click to expand...
 
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I think that is an ugly solution. Can you guarantee that the pins are ''Z before the first write?
I would define 2 of the pins as inputs, and not connect them to anything in the top entity.
Just leave mem_out(15)(2 dowto 1) as 'open' in the top entity.
 

"Can you guarantee that the pins are 'Z before the first write?"
mem_out ( 15 ) ( 2 downto 1 ) <= "ZZ" ;
if also the state at reset, so yes...

"I would define 2 of the pins as inputs"
I want the code to stay as a single vector...
 

shaiko said:
"I would define 2 of the pins as inputs"
I want the code to stay as a single vector...
Click to expand...
The mem_out(15)(15 downto 0) should of course be a single vector.
You should have the code as if the PCB error didn't exist. I mean that you should just not connect two of the bits to any pin in the top entity.
 
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    shaiko

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as far as I know,
any of the unconnected FPGA pins are pulled to a logic level (that is set by configuration pins...)
This may cause a problem!
I want them to be configured as High 'Z' outputs...
 

connect the bus as normal internally.
At the top level, drive 'Z' onto the problem pins all the time.
 
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