Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Symmetrical Output Impedance

Status
Not open for further replies.

LordSte

Newbie level 4
Joined
Jan 21, 2012
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,325
I've been reading through datasheets for various digital buffers and inverters. Few list "Symmetrical Output Impedance" as a feature. Here are a couple sheets that mention this:
**broken link removed**
On-Semi MC74HC1GU04

I was wondering if anyone can go into the specifics of this feature since I can't find anything about it anywhere. I need to interface some logic into an analog system, so I need fine control over the output impedance. I was going to try some devices with Open-Drain outputs, but that only lets you control the high-level output impedance and not the low. This "symmetrical" thing sounds interesting... Can someone explain it?
 

Symmetrical output impedance simply means equal current strength of N and P output transistors, which in practice means about doubled W/L for P transistors. You'll notice, that the output characteristic of digital logic devices isn't tightly specified. If you review vendor SPICE models, you'll find NOMI, FAST and SLOW parameter sets. Unfortunately, the process variations aren't necessarily identical for N and P diffusion steps. As a result, symmetrical output impedance doesn't mean more than symmetry for a device with typical parameters. There will be still an impedance variation.

Nevertheless using HC single gate buffers or inverters for analog purposes, e.g. drivers with defined output impedance can work, if the drivers share of the total inpedance isn't too large.
 
Last edited:
For transmitting the digital output signal over a longer line it is better to have a driver with a symmetrical output impedance(less signal distortion and line reflection). For more explanation you might look at this application article: **broken link removed**

Enjoy your design work!
 

Symmetrical output impedance simply means equal current strength of N and P output transistors, which in practice means about doubled W/L for P transistors. You'll notice, that the output characteristic of digital logic devices isn't tightly specified. If you review vendor SPICE models, you'll find NOMI, FAST and SLOW parameter sets. Unfortunately, the process variations aren't necessarily identical for N and P diffusion steps. As a result, symmetrical output impedance doesn't mean more than symmetry for a device with typical parameters. There will be still an impedance variation.

Nevertheless using HC single gate buffers or inverters for analog purposes, e.g. drivers with defined output impedance can work, if the drivers share of the total inpedance isn't too large.
So if I understand you correctly, even when using a device with a "Symmetrical Output Impedance" there can still be impedance variations (albeit smaller than usual) between the two output states. In spite of that, no matter what IC I use (symmetrical or not) I should always try to find out the actual output impedances for both logic states and see if the variation is large enough to impact my design. None of the datasheets I've looked at explicitly define these values. Is there a way to calculate them from using what is usually listed in the datasheets? Or would I have to look at the SPICE models you mentioned? I suppose I can always purchase the device and find the values using a potentiometer and a voltmeter, but that sounds super inefficient and could potentially waste money...
 

You can find out the output impedance by using a long enough line (that is represents a wave resitance for the output driver, coax cable has 50-60 ohm and twisted pair 100-120 ohm). With a fast rise and fall time of the driver you can see on the oszilloscope a voltage step function(see figure 3 in the article). Another option is to measure the output voltage of the driver with a know resistor to ground or supply voltage. The static output resistance of the driver is a voltage divider with your known load resistor.

Enjoy your design work!
 
You can find out the output impedance by using a long enough line (that is represents a wave resitance for the output driver, coax cable has 50-60 ohm and twisted pair 100-120 ohm). With a fast rise and fall time of the driver you can see on the oszilloscope a voltage step function(see figure 3 in the article). Another option is to measure the output voltage of the driver with a know resistor to ground or supply voltage. The static output resistance of the driver is a voltage divider with your known load resistor.

Enjoy your design work!
Right. I was wondering if there was another way to do it. It seems like a waste to order a bunch of parts just to measure them and find the best one.
 

If the output driver has a logic level specification(e.g. like an IH=6mA @ VH=> 2.4V, or IL=-8mA @ VL=> 0.4V) this allows you to calculate the inner resistor at that point. Dynamically it may look different, but at least you have an idea.

Enjoy your design work!
 
Because high speed digital is now all about transmission line
characteristics and good board design, having a buffer whose
Zout you can count on is a big deal. Symmetric means you
can match Zline on both LH and HL transitions. Asymmetric
means one or the other would stair-step or ring.

Hopefully the output impedance is both symmetric, and a
value which plays well with your range of achievable trace
impedance.
 
If the output driver has a logic level specification(e.g. like an IH=6mA @ VH=> 2.4V, or IL=-8mA @ VL=> 0.4V) this allows you to calculate the inner resistor at that point. Dynamically it may look different, but at least you have an idea.
Hmmm....the values in the data sheets I've been looking at aren't very tight. So after calculations I get source impedances which range from 0Ω to 2kΩ. It seems like measuring under my specific conditions might be the way to go. Also, I think I might be able to scrounge up an extra op amp from my design and use it as a buffer to avoid all this nonsense.
 

So after calculations I get source impedances which range from 0Ω to 2kΩ.
Sounds unlikely. High speed logic families (e.g. AHC) have typical output impedances in a 20 to 50 ohm range, standard HC about 50 to 100. As said, you need to calculate a process variation of up to 1:2.

Are you sure, you have OPs available that can achieve better defined impedances still valid for high speed signals, or are you mainly looking for DC and low frequency behaviour?
 
Sounds unlikely. High speed logic families (e.g. AHC) have typical output impedances in a 20 to 50 ohm range, standard HC about 50 to 100. As said, you need to calculate a process variation of up to 1:2.
Check out the **broken link removed**.
I took VOL @ Io = 100µA and did the calculations for both the typical voltage and the maximum voltage for that current. Please check my math:

**broken link removed**

Are you sure, you have OPs available that can achieve better defined impedances still valid for high speed signals, or are you mainly looking for DC and low frequency behaviour?
Good point. I believe you're referring to Figure 18. Doesn't seem like there's a problem as long as there's a decently sized series resistor after the output.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top