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Layer stack up in PCB..

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praveenlb

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Hi, any one explain clearly about how to calculate layer stackup ...considering the pin density and number of power plane,,,suppose i am using 2000 pin fine pitch bga which is 6 numbers in board..what would be the number of layer ? and why?
Praveen:!:
 

I fear, the only clear conclusion from this specification is that you'll need a larger number of layers, let's say e.g. 10 to 20. But a lot depends on the available PCB density and additional features like blind and buried vias and plugged vias (via in pad), and also on the characteristic of involved signals as speed, requirement of matched differential pairs, required signal guarding. Preferably you would want to learn this kind of advanced design by working together with experts, not just getting a few hints at Edaboard.
 
thanks for the quick replay..
yes..i got your point normally how you calculate number of layers? what are the things should i have to know ....?
thanks and regards
Praveen
 

As Fvm as stated there is no easy answer, there is a lot to learn.

Just to add some points..

1. Impedance control requirement
2. Routability- approximately a 12 X 12 array of BGA can be routed in a 6 layer card (a thumb rule)
3. Number of power rails
4. Performance specs of the PCB- EMC in specific
5. Allowed cost of manufacturability... etc,
 
shall i come to this conclusion... we cant tell exactly how many number required but considering below factor we have to assume number of layers...
Thanks and regards
Praveen
 

I don't think it is possible to calculate number of layers, it depends on too many factors as mentioned above - inlcuding component placement, pinout and PCB size (how would you define these in mathematical models?). I normally start with higher number of layers and try to use as few as I can. When everything is connected, I remove the unused layers and ask for PCB stackup, while I am still working on layout optimisation.
 

shall i come to this conclusion... we cant tell exactly how many number required but considering below factor we have to assume number of layers...
Thanks and regards
Praveen

No..no...no... You can still accurately estimate the layer count. But that can be done once the schematics is completely done and you import the netlist to CAD. After everything else in the PCB are fixed- that is Schematics, board geometry and placement of major components- you can accurately predict the number of layers and complete the routing..
 

Part of the skill of a PCB designer is being able to work out the required number of layers, this will become easier with experience and study. There are numerous threads on this site with quite comprehensive links to reading matter, I would have a look around.
 

If some one ask same question in interview what would be the answer ..?
same question asked for me....i gave the explanation , but he is not ready to listen....is he dumb??

Praveen
 

Hi Praveen,

Its really difficult to answer exactly to calculate the layer stackup for a pcb. But it mainly depends on ;
1-number of I/O's in design & impedance requirements
2-number of Device pins
3-number of power supplies & current ratings
4-Your design complexity with component used
5-Your Fabhouse capability (using blind & buried vias)

regards
SA
 
Praveen, if you explained what we have stated and he didn't listen then he cant have done many PCB's, or is just some management type who has read a book or two.
You can approximate the layers required as we have all said above, but you have to look closely at the design, power supplies etc etc.
 
Hi, any one explain clearly about how to calculate layer stackup ...considering the pin density and number of power plane,,,suppose i am using 2000 pin fine pitch bga which is 6 numbers in board..what would be the number of layer ? and why?
Praveen:!:

Assuming you are using a processor and memories in your board. You can estimate the minimum number of layers by checking on how many layers are needed to fan out all of the signals in the processor, after determining the minimum number of layers to fan out signals, check if you can satisfy the impedance requirement needed in your memory, if not, add layers to satisfy it.
 

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