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steup time and hold time calculations

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vimalraj205

vimalraj205

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setup time and hold time calculations

hai everyone,
i am new to STA can anybody say why Setup is checked at next edge of the clock and hold is checked at same edge of the clock and can anyone clearly say about that calculations :???:

plz help me to know about that......................
 
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hi vimal,

Data enters into flop only at the positive edge of the clock.but data does not enter as soon as pos edge arrives..so we set a time before a pos edge (next edge) occurs..but in case of hold we used to hold the data till next edge arrives sowe check it at the same edge...
 
Hi Vimalraj,
setup time:-The amount of time required to be stable before arrival of clock edge is called as setuptime
tcq+tcobi<=tclk-tsetup so,in set up time the setup time is calculated at the next posedge of capture clock from first posedge of launch clock

Hold time:-The amount of time required to be stable after arrival of clock edge is called as holdtime
tcq+tcombi>=thold so,in hold the hold time is calculated at the same edge of capture clock from launch clock

With Regards,
D.Raviteja
 
when RTL is written, They would assume that , data will be passed between the registers, with respect to clock edges, i,e one edge launches data on q pin of ff then by next edge only the next ff should capure/read it.

setup time check makes sure that, when next clk edge reaches the ff2, data will be ready at the ff d pin, if its not ready before clk arrives, then flop may go to metastability mode, where we can't assure the o/p of the flop.

hold time assueres that , the launched data from ff1 will not be caputre in the same edge of the clok
 

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