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Recent content by zjwywn

  1. Z

    fast clock signal to slow clock signal transfer - 2 questions regarding clock domains

    Q1. I think you didn't show us the length of the signal to be synchronized, this is important in choosing synchronization technique. Refer to https://www.fpga4fun.com/CrossClockDomain.html for detailed information. Q2. If you are sure about when the address bus get stable , and the address bus...
  2. Z

    How to test delay time with FPGA?

    Thank you very much ! You mean I can choose 100M Hz clock as the working frequency. I want to use Spartan3AN device as the processor, using a 133 MHz clock oscillator installed in the auxiliary clock oscillator socket. Does it work ? Best regards.
  3. Z

    How to test delay time with FPGA?

    Nowdays we are designing an ATE, there are two signals A and B,we need to test the dalay time of signal A after signal B falling low. It is easy to test it with oscilloscope. My question is how to test the delay time with the help of FPGA device ,and which family device should I choose? After...

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