How to test delay time with FPGA?

[zjwywn]

Nowdays we are designing an ATE, there are two signals A and B,we need to test the dalay time of signal A after signal B falling low. It is easy to test it with oscilloscope.

My question is how to test the delay time with the help of FPGA device ,and which family device should I choose? After signal B falls from 3.3V to 0V, signal A will change from 0V to be a pulse signal , the frequency of A is about 200K Hz.

Can somebody tell me how to realize it ? We will design the test board by ourselves.

Thanks !

 

[FvM]

The answer depends on the intended measurement range and resolution. Counting delay time with 5 or 10 ns resolution is a trivial task in terms of HDL programming.

 

[zjwywn]

Thank you very much !
You mean I can choose 100M Hz clock as the working frequency. I want to use Spartan3AN device as the processor, using a 133 MHz clock oscillator installed in the auxiliary clock oscillator socket. Does it work ?
Best regards.

 

[FvM]

133 MHz should be fine for delay counting. You can also generate a different timebase with the Spartan 3AN PLL ("DFS").