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Re: Clock Uncertainity
Theriotically, the maximal frequency is (1/0.7)GHz
clock uncertainly always be used to estimate the clock skew or jitter or reserved margin
usually, circuit highest frequency is determined by the critical path...
sdf $width check tcheck limit
because some IP clock width check value in SDF is wrong, so can i turn off these IP width check when SDF annotation? we can not hack the IP verilog library now...
and we are running it with NCsim.
Thanks
Yes, notimingcheck can solve this issue, but it is a global option and it will turn off setup/recoveray/removal too, i just want to turn off "hold" check and i am not planning to turn off all timing check :cry:
timingcheck vcs
i am trying to do a simulation with a pre-CTS sdf, so i am forced to hack the clock tree cell delay and interconnect delay to 0, but it will cause hold timing violation on DFF, so, how can i turn off "hold" timing check in ncverilog? i know, i can make sdf annotator ignore hold...
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