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Recent content by zermelo

  1. Z

    vsim-3170 error: Could not find...while simulating Altera NCO IP

    Hi , I am quite new to Altera (Xilinx /Actel guy up to date) and I am trying to simulate an Altera NCO IP with frequency modulation input to see its frequency resolution performance. I wrote the following .do file...
  2. Z

    Strange behavior when reading ROM data in Altera

    Hi , I am looking at o_chirp50k in the simulator. Actually , the memory array in Modelsim displays already incorrect values (is there any other way to check the stored values, for instance in Quartus?) By the way, i have been reading online. Looks like Quartus does not support .MIF with signed...
  3. Z

    Strange behavior when reading ROM data in Altera

    Hi, I have used MATLAB to generate a linear frequency modulated waveform, quantize it as signed 16 bit and write it into a . MIF file: for i = 1:N fprintf(fid_50,'%i : %i;\n',i-1,(Chirp50_n(i))); fprintf(fid_200,'%i : %i;\n',i-1,(Chirp200_n(i))); end So I have a two . MIF files...
  4. Z

    [SOLVED] Active Serial JTAG debugging in Cyclone II

    I might have read too fast the last part of the other thread. Thanks for the reminder. That's why I am asking. It is easy to understand that you cannot use a JTAG that is not connected to the FPGA:) Jose
  5. Z

    [SOLVED] Active Serial JTAG debugging in Cyclone II

    Hi, I have a PCB with a single JTAG header connected to an EPCS4 device. In that same PCB, there is a Cyclone II EP2C8T144C8N that I can program using Active Serial mode through the flash. When I select JTAG in the programmer there is no device found. When I do the same in Signal Tap there is...
  6. Z

    [SOLVED] VHDL: Unknown post implementation behavior of signed fixed defined signals

    Hi, Thanks for the discussion. The problem has been finally solved. A misunderstanding of the FPGA input (frequency selection signals) was in the end the root cause. A linear interpolator was interpolating always to zero . That combined with the ROM optimization described above was the cause...
  7. Z

    [SOLVED] VHDL: Unknown post implementation behavior of signed fixed defined signals

    I have a JTAG head in the board, that is connected to the EPCS4. When I select JTAG in both the Programmer or the Signal Tap , I do not get device found. My only option is to select Active serial mode in the programmer, select the .pof and program the EPCS4. Am I missing something? Jose
  8. Z

    [SOLVED] VHDL: Unknown post implementation behavior of signed fixed defined signals

    Hi, Thank you all. I solved the problem of the memory optimization . As Tricky pointed out , it had to do with an undriven output upstream. Have put a noprune attribute on that and now the ROM is in place and initialized. But still I have my two outputs tied to ground when I test in the board...
  9. Z

    [SOLVED] VHDL: Unknown post implementation behavior of signed fixed defined signals

    Hi, I tried method 1 (.mif attribute). Here is my definition: signal s_hmg: mem_type_hamming; attribute ram_init_file : string; attribute ram_init_file of s_hmg: signal is "Hamming_10ms.mif"; I edited the .mif with the Quartus Memory editor , to get the .mif standard format. You can find the...
  10. Z

    [SOLVED] VHDL: Unknown post implementation behavior of signed fixed defined signals

    Hi, Now that you point that out...I think I have used method 3 in this same design for another ROM:) You are right, s_hmg should not be a signal, but a constant or not to exist at all in the code. I´ll try that tomorrow and post the feedback. By the way, could you provide an example of method...
  11. Z

    [SOLVED] VHDL: Unknown post implementation behavior of signed fixed defined signals

    Hi, Yes, I know how to preserve individual signals after synthesis. In fact, I am close to the root of the problem. In this design , I want to use a 1024x16 bit ROM for the Hamming window samples. This ROM is read in the following process: -- P_WDW_SPL: The window si sampled to match pulse...
  12. Z

    [SOLVED] VHDL: Unknown post implementation behavior of signed fixed defined signals

    Yes, I am using it to deal with the problem . I found that I have two outputs in a subcomponent that are not used , but I just wrote the VHDL to simulate it. I want to keep that VHDL, and I am trying to use the noprune attributte in all he signal chain that drive those outputs. But I might...
  13. Z

    [SOLVED] VHDL: Unknown post implementation behavior of signed fixed defined signals

    Hi, Hmmm. As easy as that , I should be measuring s_ttl_high_sfx to see if the conversion is failing. The code and the FPGA project is propietary , its part of an R & D activity that will become a product later. I will check with management. In any case, I would send you the project to your...
  14. Z

    [SOLVED] VHDL: Unknown post implementation behavior of signed fixed defined signals

    Hi Tricky. I remember you helped me out with a linear interpolator implementation some time ago. That s_ttl_high_sfx is the output of that interpolator, which I decided to implement as signed fixed for the purpuse of reusability.s_ttl_high is defined as unsigned because it has to be compared...
  15. Z

    [SOLVED] VHDL: Unknown post implementation behavior of signed fixed defined signals

    Hi all, I am working with a transceiver board to implement a Hamming windowed Chirp (linear frequency modulation) transmitter into a Cyclone II. Due to economic issues, instead of loading values into a DAC, we are using a dual MOSFET driven by complementary TTL signals to control the...
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