Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by yusq

  1. Y

    fsdb dump of signals in 64 bit mode

    Now ncverilog version 5.1 support 64bit mode. However, Nova pli seems does not support 64bit mode, which leads to that I can not use $fsdbDump to dump signals in 64bit mode. Of course, I can use vcd dump method. As you know, the vcd file dumpped is too large. Is there any other way to solve the...
  2. Y

    What happens if timescales are different in different files of the same design?

    include timescale verilog I think no problem if all of the files (including the libraries) has timescale. However, if the verilog library( with time infor) does not contain timescale information, the order of the files may have effect on the simulation results. however, the larger the...
  3. Y

    LDV 5: can't find ncvlog.exe error!!

    indeed, the program ncverilog is not a binary, you can open the script and see what happens to you. maybe you miss the CDS_ROOT variable, maybe just the path in you ncverilog to ncvlog.exe is not correct. Please check it and I think you will find the correct answer.
  4. Y

    what is a buffer and other questions

    Re: what is a buffer? see buffer in layout, it is really two inverters. the size of buffer is just the W/L of your process which may vary in drive ability. we use buffer to do CTS, to fix high fanout net , to fix long wire etc...
  5. Y

    Primetime or DC in writing SDF ?

    of course PT, it is a presto standard in EDA to do STA. we use PT to tapeout several chips.
  6. Y

    Value change dump file

    vcd value change dump format when you debug you functionality, you should choose fsdb. but when you still consider power analysis, you should choose VCD. however, VCD file is two large.
  7. Y

    [SOLVED] Which is the best layout tools?

    virtuoso, I think. and we use it for many years.
  8. Y

    How to know the net name connecting port/pin in DC shell?

    the synopsys document states this very clearly.
  9. Y

    how to check the functionality between cdl and verilog RTL ?

    i know CONFORMAL LEC, however, when you use lec to extract a large circult, it is very difficult to debug. The lec will generate some logic such as the ff with set & reset tie to 0 etc...
  10. Y

    how to check the functionality between cdl and verilog RTL ?

    the circuit guys design the circuit according to the spec. on the other hand, front guys write the RTL code according to the spec. how can you verify they function the same. You know simulation is not a good way because you have to take a great effort to compare the two result between the...
See more

Part and Inventory Search

Back
Top