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Recent content by ymli

  1. Y

    suggestion on IC front-end design

    Genrally, only when you are in the industry you will find what are useful for you. In my opinion, the most important is how to manage a project and how to communicate with the other guys.
  2. Y

    Scripts for EDA, scripting techniques (perl, tcl/tk etc)

    Scripts for EDA... Python is a pretty good choise to develop script. 1. it is free 2. it is OO 3. There are tons of person use and contribute to python 4. it is platform-free
  3. Y

    How to implement interpolation using verilog coding

    verilog interpolation It seems nemolee needs a synthesizable design. you may google the things you want first, maybe you get some clues.
  4. Y

    Static timing analysis and Dynamic timing verification

    Dynamic means the internal states in a circuit change, then you need input vectors to drive the circuit. Static means the internal nodes keep unchange in the timing analysis process.
  5. Y

    what tools used in system-level verification

    There is not a general answer for this question. It depends on the complexity of the job, the resource you may use. of course your habit at the same time.
  6. Y

    Looking for free PIC C or ASM compiler

    Free PIC C compiler Is there any free PIC C compiler or ASM compiler on the net? Thanks in advance.
  7. Y

    Gate count for various building blocks

    The gate count also depends on the target library you use if you use the standard cell library.
  8. Y

    How to avoid bugs of tools ?

    How to aviod tools bugs? my experience is using the stable version, not the newest version.
  9. Y

    What do you gain from Verilog2001 ?

    Actually I forget the new features of Verilog 2001 for the compatiblity reason.
  10. Y

    Verilog/VHDL editor in linux

    vi verilog mode I do believe EMACS is the best editor, which has the auto-file features, and it is very useful when you edit a complex design.
  11. Y

    EMC/EMI/EFT issues in logic level

    emi problems Hi, Is there any guidance to avoid EMC/EMI/EFT problem in logic level, ex: when developping the RTL verilog code. Thanks
  12. Y

    Hi,i want to know how to write good testbench,thank you!

    when you log in, you may find how much points you have. In order to increase the points, just contribute something, post, reply. then you will have enough points to download the books
  13. Y

    Can anyone provide Synthesis Checklist

    checklist for successful synthesis Can anyone share his/her checklist for logic synthesis with DC? If possible, checklist for each step of SOC design. THANKS
  14. Y

    who is familiar the event-driven simulation?

    There are 3 kinds of logic simulation: Event-driven compiling mode Cycle-based You may refer the simulator manual (ex. NC-HDL, VCS, ...)
  15. Y

    Where to start designing in ASIC?

    asic designing you may also google some tutorial on the web. ex. many university courses
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