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Recent content by yli

  1. Y

    simple question about body effect.

    Hi all: For a diode-connected load, why the input impedance seen at the source of NMOS is lower when we consider the body effect. If we don't try to derive the equation, do you have any intuitive explanation? Thanks
  2. Y

    PLL jitter ang phase noise

    pll jitter simulation Use ADS can easily draw the eye diagram and There is jitter histogram in ADS design guide. I think this may measure the jitter; however, I don't know how to setup the measurement. Do anyone know that?
  3. Y

    How to simulater Oscillator

    I think that the close loop gain of the Oscillator is smaller than 1. Then the oscillation will stop after a period of time.
  4. Y

    How to use ADS to measure jitter?

    Could anyone know how to measure the rms jitter in the ADS?
  5. Y

    How to use ADS to measure jitter?

    hi all: I know that we can draw eye diagram at ADS and we can measure the peak to peak jitter directly from the width of the trransition. And if we want to measure the rms jitter, we have to use the jitter histogram in the ADS. The attachment is the jitter histogram in the ADS. I don't...
  6. Y

    ask about the comparisons between LC VCO and ring VCO

    LC ring Jitter Small Large Tuning range Narrow Wide Control Single-ended Differential Area Large Small
  7. Y

    how to compute the phase noise in ADS and display it?

    Re: how to compute the phase noise in @DS and display it? I only know that you can use "Oscport" in the ADS to measure the phase noise. I don't know the detail of it. Do anyone know it? Thanks
  8. Y

    eye diagram in hspice

    hi all Could you tell me how to draw the eye diagram in hspice? thank you
  9. Y

    What is the normal BER for 2.5 Gb/s CDR?

    hi all: If I want to design a 2.5Gb/s CDR circuit, what is the normal BER? Is that 1e-12? Then how do I calculate the jitter spec of the VCO? Thanks a lot
  10. Y

    CDR with half rate PD Question

    half-rate phase detector hi all: I try to refine my question. The problem of my CDR circuit is that the Bit error rate is too large, which is 1e-3. For the 2.5G CDR with half rate PD, it should be smaller than 1e-6 or even smaller. I think that the problem would be result from the VCO. I use...
  11. Y

    CDR with half rate PD Question

    phase interpolator cdr hi all: Pardon my ignorance. I have a question about CDR, please give me some advice. I have designed a 2.5G CDR with half rate PD. I follow the Razavi paper, A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector, May 2001. This CDR...
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