Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by yiyen

  1. Y

    HFSS RF IC transformer issues

    Re: mutual inductance hfss Hi, I happen to be working on the same project now on a 90nm process. I am also using HFSS to create a step up transformer. I used the formulas above for computing L and M and the values I am getting are perfectly reasonable. My problem now is, I don't now how to...
  2. Y

    CMOS transformer creation (6-port)

    Hi wccheng, Have you already figured out what simulator to use? I am also encountering the same problem. Thanks in advance! yiyen
  3. Y

    ADC of Zilog Microcontroller

    Hi akoangsimula, For your hardware problem, I think IRC Slimboard can help you. :) IRC SlimBoard Just investigate on it. Your hardware problem is already addressed by that product. That is available here locally. Hope this helps.
  4. Y

    zilog microcontroller

    Hi akoangsimula, Your project is fairly manageable especially when one has fully understood the concept of ADCs. You should think of a way to "quantize" the output voltage. After this quantization, the output of the ADC (bits 0s and 1s) should be used in your program (a look-up table, if you...
  5. Y

    a question about defining layer in HFSS

    Hi yfluo, How did you solve your problem? Because I am also stuck with this one. Thank you and I hope you can reply. Yiyen
  6. Y

    [SOLVED] LVS problem on Customized transformer layout

    Problem solved. I used the LVS_BOX command.
  7. Y

    Calibre PEX rule file

    If I get it correctly, you are using the DRC rules file for your PEX run. Is that true? Sorry if I misunderstood your statements.
  8. Y

    Calibre PEX Error--Inductance engine were not properly built

    Hi all, I'm currently running Calibre PEX to extract my layout. I've seen that there is an option to include mutual inductance in the extraction. Since my layout has inductors in it, I would like to take advantage of this option. However, when I extract using this setting (L+M, self+mutual...
  9. Y

    [SOLVED] LVS problem on Customized transformer layout

    Thanks for your suggestions! Will read that VPCD guide. Update you later =)
  10. Y

    [SOLVED] LVS problem on Customized transformer layout

    Hi all, I am now designing integrated transformer power combiners using MOS. Unfortunately, our libraries (IBM CMOS9FLP,9RF) do not include built-in transformers so we need to design and lay them out manually. [Question 1]: Upon putting a dummy instance in schematic, placing coil layers in...
  11. Y

    Post-layout simulation

    thanks erikl for your documentation! it really helped me solve this issue. thanks!
  12. Y

    [SOLVED] Power amplifier attenuation

    Solved! I checked the port arrangement in my spice file and found out that my output and input ports are interchanged. That means I was matching the wrong network.
  13. Y

    Post-layout simulation

    hi! i'm having the same problem, do you have any update on how you solved your problem? Thanks!
  14. Y

    [SOLVED] Power amplifier attenuation

    hi vfone, by multi-pole input matching network, do you mean ladder LC network? thanks!
  15. Y

    [SOLVED] Power amplifier attenuation

    Hi edaboard members! I am currently designing a Class AB Power Amplifier (in 90nm cmos process) operating at 5.8GHz. In my initial design (which consists of transistor, rf inductor choke and dc block capacitor at the output), I obtained a Power gain of 12.26dB. However, when i implemented the...
See more

Part and Inventory Search

Back
Top