yiyen
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Hi all,
I am now designing integrated transformer power combiners using MOS. Unfortunately, our libraries (IBM CMOS9FLP,9RF) do not include built-in transformers so we need to design and lay them out manually.
[Question 1]: Upon putting a dummy instance in schematic, placing coil layers in Virtuoso, and defining ports in both the schematic and layout views, I get an LVS error like this (DRC showed no errors): Nothing in source. Nothing in layout. Corresponding cells could not be identified. What could be the problem here? I've read that as long as the number and name of ports in schematic and layout views are the same, correspondence can be achieved and no LVS errors would occur.
[Question 2]: In case I am doing it wrong, are there other ways that allow you to create your own transformer, extract its parasitics, obtain its efficiency, have its "symbol" view and use it to connect it to the other part of the circuit, and simulate the circuit as a whole entity?
Thank you very much for your help. :|
I am now designing integrated transformer power combiners using MOS. Unfortunately, our libraries (IBM CMOS9FLP,9RF) do not include built-in transformers so we need to design and lay them out manually.
[Question 1]: Upon putting a dummy instance in schematic, placing coil layers in Virtuoso, and defining ports in both the schematic and layout views, I get an LVS error like this (DRC showed no errors): Nothing in source. Nothing in layout. Corresponding cells could not be identified. What could be the problem here? I've read that as long as the number and name of ports in schematic and layout views are the same, correspondence can be achieved and no LVS errors would occur.
[Question 2]: In case I am doing it wrong, are there other ways that allow you to create your own transformer, extract its parasitics, obtain its efficiency, have its "symbol" view and use it to connect it to the other part of the circuit, and simulate the circuit as a whole entity?
Thank you very much for your help. :|