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Recent content by ygggliu

  1. Y

    What's the best VHDL/Verilog/SystemVerilog editor?

    pspad vhdl UltraEdit is best in windows, and vim is best in linux
  2. Y

    two source clock in DFT mode

    using multiplexer selected by test_mode, the two clock domain will be merged.
  3. Y

    Gate-level Netlist TO RTL Netlist

    gtech netlist the synthesis tools(Design Compiler) can help you transform the gate netlist to any process.
  4. Y

    DC output file usage and the full name of these file

    SPF is test protocol of DFT for TMAX input. SPF,Stil Procedure File
  5. Y

    Anyone Can Share Synopsys IC compiler Online PDF files ?

    Hi, xreaver Can you email the PDF to me? my email: yggg.liu@gmail.com
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