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Recent content by yfeng

  1. Y

    FPGA Verilog problems

    oh, yes,you are right, I comprehend it now. I consider the "else" block including the following three expressions. I am wrong. Thanks guys.
  2. Y

    FPGA Verilog problems

    thanks to your caution,but I mean ,since "clkout3<=1" executes after counter==2,why "clkout4<=1","clkout5<=1" don't.
  3. Y

    FPGA Verilog problems

    oh,yeah, it works well,thanks. I still puzzle on the question: In the else block,if no begin/end,why clkout3 still ouput clock? if the expression in else block clkout3<=0; works, should the next two expressiones be valid? such as clkout4<=0; clkout5<=0;
  4. Y

    FPGA Verilog problems

    yeah, i hope to get the same width pulse as the clock input in the output,such as these picture From these pictures, you can see different codes' simulation. Apparently, using three "always" structures clkout3 ,clkout4 and clkout5 have outputes, but one structure only clkout3 outputes. What's...
  5. Y

    FPGA Verilog problems

    hi,everyone, I want to design a frequence divider, the dividing ratio is 2000; It has a clk input and three same clock outputes, when i use modelsim-Altera simulation,problems come, there are only one clock output,others are zeros;however,when i use three always structure ,the output is all ok;I...
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