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what frequency does the DAC work? and You can read some papers from Sansen's group. The key is the arrangement of the curren source array and the decoder arch. if it works at high frequency, the low power design of the decoder is not trivial.
Re: Ring oscillator
you can simulate the open loop ac gain of the delay cell chain, and find wether it is large enough for start-up.
a simpler method is set the running step of tran small enough--less 1/10 period, and the noise of the numerical computation in simulator will make it oscillate...
it is really great!In the software and digital disign field,there are lots of sucessful samples--such as linux and opencores.org
but there is some different for analog and RF,because it is too detial or somewhat else,so maybe we should try to think clearly that what kind of design is fit for...
symmetric load high freq
for this delay cell it's not diffcult to archieve the target,maybe you can add a voltage regulator for VCO to archieve high PSRR
when i use laplace_nd function of verilog-a in hsim simulation, it cannt work,but using spectre simulation works well, what's the problem?
i mean that when using hsim,the result assigned with laplace_nd will not change,it hold a constant
my hsim is version 5.0 in linux.any one else met the...
i think that when you design your protype, you'd better use a filter with off-chip device--so that you can easily adjust your bandwidth when you debug your design.
But when we do mass production,we would like to use on-chip filter for lower cost.
Re: How to put IO pads
Teddy:
you said that just use last metal.do u mean that in the layout,do not full of the pad with each metal just as usually we do,in order to reduce the capacitive load?
but i wonder that for the PAD the most of the load of it is the ESD circuit,so maybe i have to make...
Re: How to put IO pads
For high frenquency output,such as pll's output,can we use a PAD without the big capacitive load-ESD?How usually people design a PAD for RF purpose?:D
Re: How to put IO pads
In the prototype system design,can i just open a window for I/O connect and without ESD for output signal in order to output the signal at high frequency?
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