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present a model for you:
//------------------Load file(Binary/Hex)----------------------------------------
reg [11:0] data_mem[0:16384]; //define a 12bit*16384 array
initial
begin
$readmemh("adc.txt",data_mem); //load data to data_mem
end
In hardware the function of pipeline is implemented by inserting registers in the combinational logic. Long combinational path tends to cause low maximum frequency. If there is critical path in your design, you can use the pipeline to insert registers in the long combinational path to shorten...
suggestion:
firstly ,a blinking LED project;
then,a 7-segment led project;
then,a serial port project
....
when u complete the 3 project,u should get clear with FPGA design.
For referrence!
it is not a tough task in logic design world.
For ur example,u can use a FSM(Finite State Machine) to implement the design.
And FSM is just one way to complete ur task.
For a starter in logic design,FSM may be the better solution.
But firstly,you should know what is a FSM?and how to write a...
a suggestion:from a robust design vision,u should use a synchronous circuit to do the communication between FPGA and DSP.
for ur example,maybe it's better to use follow code:
always @ (posedge clk)
if(rd_valid)
....
and the rd_valid should come from a edge detect circuit which detect
the neg...
if u want to use edge and level sensitive in a same block,maybe you can use a edge detect circuit to detect edge sensitive signal,then you can turn it to level sensitive.
i think it is not good to use the combination combination of edge and level sensitive events .just for discussion
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