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Thank you very much for the reply.
I haven't decide the interface standard of my chip yet, because it'll depend on the test equipment. I'm exploring the possibilities. If I use a signal generator, I'll have one type of interface on my ASIC. If I use some FPGA evaluation board, I'll have other...
Hi all,
I have a very straightforward requirement:
I need to test my own chip (ASIC).
1st step: Load data from my computer to a RAM. The data width is at most 32 bits. This process does not need to be very fast.
2nd step: Read the data sequentially from the memory and give the data to my chip...
Hi folks,
I have a very large netlist, so the simulation is very slow. Now I want to configure Calibre PEX such that it ignores some resistance below a given value to reduce size of the netlist.
Is there any way of doing that? Any switch I can turn on or any threshold value I can set in Calibre...
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