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Recent content by xinsu

  1. X

    how to reduce cell leakage power in large design

    if part of design do not use in some application board,you can chose low power methedology to power off these parts to redues leakage power
  2. X

    low power technics in rtl synthesis

    you can reference low power constraint CPF(cadence) or UPF(synopsys) documentation.
  3. X

    Hold fix issue - hold violation problem

    Hold fix issue check your input delay constraint in sdc,maybe it's un-resonable.
  4. X

    flipchip & wire bound

    these are two types of bound,just depended on power consuption.
  5. X

    Timing optimization of scan paths

    normally,scan shift/scan capture constraint will cover scan path,if you just want optimize scan path,you can use these constraint to opt design,but you should be careful donot touch function path
  6. X

    glitch - What is glitch analysis? explanation

    glitch you can see STA tool manual of CTE/pt for details
  7. X

    Different processes with the same process size

    If you can study the different vt layout,you can have more details
  8. X

    crosstalk after post routing

    If you just implement in project,the ways will be supplied by EDA vendors,and now,you list the main ways used in EDA tools,but if you want research,I recommend you can search this in IEEE website.
  9. X

    How do you balance Generated clock?

    Use clock groups as I said above
  10. X

    Causes of Setup violations

    1.constraint is too loose or covered 2.Place is not right 3.design is not available
  11. X

    reg to reg violation for hold violations in soc encounter

    if you met hold vio,you'd add more delay for datapath,normally tool have this feature to do(optdesign in encounter),maybe left fewer in final opt,and you have to do it by manual
  12. X

    Help me to set clock metal layer preference!

    Clock Routing for layers,you'd better chose 2 continuios layers,for route priority,you'd better route ahead of other signals.
  13. X

    what are the different types of drc errors we get after nano

    for space vio,sometime because library issue,such as blockage issue
  14. X

    How do you balance Generated clock?

    generated clocks cts I think your question is not clear,if you want balance all generated clk,you can define clock root pin if they generated from same source,and you can define clock groups if they come from different souces.if you just want to balance part of generated clock,you should...
  15. X

    How to design ( a.(b+c))' using CMOS?

    cmos layout2 firstly you should chose schematic to connect with your funcation,then draw it in layout
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