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Hi vbhupendra
Why should we use highest division ratio? You mean that we should use worst case for phase margin? Then if we use transfer function to do analyse for total pll, which division ratio should we use?
thanks very much!
We need to provide extra oscillator to generate reference frequency.
Only one crystal can not oscillator.
The oscillator circuit is not complex. Simply it can be implement with one INV, one crystal and two capacitors.
Re: hspice problem ,too
Maybe, in 0.18um model,
the formula i=β*(vgs-vth0)^2 is not accurate.
so if you use i1/i2=(vgs1-vth0)^2/(vgs2-vth0)^2 to get vth0, it may also not accurate.
In Hspice, you can use
.probe dc LV9(m1)
to get vth.
Re: Ring VCO
As I know, the differential ring osc can use even number of inverters. In razavi book you will find it.
Because in differential,the output can cross put to another inverter's input, so the phase can satisfy the Barkhausen's law, then it can oscillate.
dithered pll
I am also confronted with this problem.
when I put signal Xin[k]=0.5+0.25*sina(100*k/pi)
into to MASH 1-1-1 sigma-delta modulator, I can see the noise in low frequency is moved to high frequency. But when I put MASH 1-1-1 sigma-delta modulator in F_N PLL, I don't find it works...
Re: plls and simulink
I have made a model of sigma delta frational n pll in matlab simulink,but I don't
find sigma delta f n pll is better than classic f n pll. My model of classic n pll works well.Maybe my sigma delta model has some errors. Who can explain why?
PLL Spurs
Spurs can also appeared by the reason of PFD's dead zone.
If the phase error is too small, the PFD can not detect it, then the control line of VCO will not constant, and the spurs are formed.
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