Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
hi, when our design growing big, there so many registers to control chip function.
which soft tool do we select for manage registers.
as i know is:
Duolog Technologies : BitWise
Denali Software : Blueprint
Semifore : srCompiler
where can download these tool.
or do we have more choose...
i am work in digital group project , need change Spice to verilog netlist , so that i can simulate only need digital simulator tool , like vcs , modsim
which tool or program can change Spice to verilog netlist
thank you
spice to verilog perl
i am work in digital group project , need change Spice to verilog netlist , so that i can simulate only need digital simulator tool , like vcs , modsim
which tool or program can change Spice to verilog netlist
thank you
dc sweep gm plot cadence
When the short-channel (0.35u), Vth is not constant, it is the function of Vgs. now I want to do Vgs dc scanning, plot Vth vs Vgs graphics, how can I plot this in cadence? I spent a few hours last night,but i did not find Vth. Hspice there is .Probe par ( "vth")
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
