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Recent content by wwwww12345

  1. W

    " Calibre + hspice " post-sim netlist pin name problems

    I have known the reason of upper problem, but I donnot know what the colon meaning in the latter hspice netlist, c9999 N_noxref_GND18:_c_123489_p net2 10f Who can tell me ? thank you !
  2. W

    " Calibre + hspice " post-sim netlist pin name problems

    Hi all, I use calibre + hspice as post-simulation tool. I got post-sim netlist by calibre , it is as : .subckt ana_top VSSA VDDA GND18: 7 VDD18: 9 10 11 12 ...... ..... But in this file and attached .pex and .pxi file, I found all pins except GND18 and VDD18 . They do...
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    Help me with hsim co-sim, digital block not replaced

    Hi, Since I have to do co-simulation with HSIM, I make a very simple netlist as : global 0 vdd! XI4 (vinvin vout) invv C0 (vinvin 0 ) capacitor c=1p R0 (vdd! vinvin) resistor r=100K V0 (vdd! 0 ) vosource type=pulse val0=0 val1=1.8 period=1u width=500n...
  4. W

    How to model UTP cat5 cable in gigabit phy simulation?

    Hi all, please tell me how to model cat5 cable in 100/1000M ethernet PHY transmitter simulation , I am pullzed in this for several months. IEEE 802.3 only gives 10M cable model , but it doesnot fit for 100/1000M. Thank you in advance!
  5. W

    How to simulate 100/1000M ethernet line driver spec

    According to University of New Hampshire's relevant documents and IEEE 802.3 standard, I found a lot of specs to simulate. Can anyone give me the guidance how to set up the simulation environment in candence? Thank you very much!
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    How does wilson current find its DC working point?

    For a normal current source , we first have a current , then the current flows through a dioded connected mos and generates a voltage vx, so vx makes M0 generate a current. But for a wilson current mirror, how does it generates vy and vz ? Only formula forces these two nodes to be the correct...
  7. W

    help me calculate the slew rate

    Hi tshah, Thank for your reply. Can you tell me why SR>2*pi*f*V(peak)? Let us turn to this problem. If we look the schematic as a two stage opamp, the first stage SR is Ibias/C, while the second is Itail/Cout. How can he calculate the formula 1? Can someone tell me ? thanks !
  8. W

    help me calculate the slew rate

    Hi all, I donot know how the slew rate in this paper is calculated . Does anyone know , please tell me ,thank you!
  9. W

    Help me find the error in spectreverilog sim

    Oh, I have solved this problem . If I dis-selected the "select all digital node voltages" , the tran sim will go through. Maybe something wrong with the Interface elements.
  10. W

    Help me find the error in spectreverilog sim

    Hi all, I am using spectreVerilog to take a mixed-signal simulation. But when I ran transient sim, the error comes out in the log as in the picture, it says :"component name (vnex5 and vnex5 ) not declared"; and the netlist writing the vnex5 and vnex5 is in the picture too. Does anybody know...
  11. W

    why bigger VDS introduces bigger rout (small signal)?

    o , I got it ! We can differentiate ids to VDS, then the problem solved.
  12. W

    why bigger VDS introduces bigger rout (small signal)?

    For a first order approximation, rout has no relation about VDS. Anyone can tell me?thanks!

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