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# How does wilson current find its DC working point?

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#### wwwww12345

##### Member level 1
For a normal current source , we first have a current , then the current flows through a dioded connected mos and generates a voltage vx, so vx makes M0 generate a current.

But for a wilson current mirror, how does it generates vy and vz ? Only formula
forces these two nodes to be the correct voltage? Can anyone tell me ? thank you in advance.

The Wilson Current mirror doesn't provide much advantage when using MOS. It's biggest strength is eliminating base current error when using BJT's.

However, here's how it functions in your configuration:

Assuming initially all devices are off, the following sequence of events will happen during start-up:

1) I4 will start increasing voltage vz.
2) When vz > VT, M5 will start increasing voltage vy.
3) When vy > VT, M3 will start to conduct current. It will keep increasing until it sinks all of I4.

The net voltage will be:
vy = vgs of M3 necessary to pass all of I4 current.
vz = vy + vgs of M5 necessary to pass all of ratioed current in M4. So if M4 = M3, it will be the vgs necessary to pass I4 current.

ecc008lty

Points: 2

### ecc008lty

Points: 2
The Wilson Current mirror doesn't provide much advantage when uesing MOS
It also has a cascode enhanced output resistance, may be a srious advantage in some applications.

gszczesz said:
The Wilson Current mirror doesn't provide much advantage when using MOS. It's biggest strength is eliminating base current error when using BJT's.

However, here's how it functions in your configuration:

Assuming initially all devices are off, the following sequence of events will happen during start-up:

1) I4 will start increasing voltage vz.
2) When vz > VT, M5 will start increasing voltage vy.
3) When vy > VT, M3 will start to conduct current. It will keep increasing until it sinks all of I4.

The net voltage will be:
vy = vgs of M3 necessary to pass all of I4 current.
vz = vy + vgs of M5 necessary to pass all of ratioed current in M4. So if M4 = M3, it will be the vgs necessary to pass I4 current.

Thank you , gszczesz! I got it .

it is a shunt series feekback,with the M5 as amplifier and current mirror formed by M3 and M4 as its feedback network.The beta is set by M3 and M4

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