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I saw some example of buzzer applications. they are not directly connected to microProcessor's IO pin, but through a transistor, and higher voltage on transistoe's collection pole, the buzzer is parallel connected with collection's resistor.
May I just simplify by connect microProcessor's IO...
New to DSP
I am DSP newbie.
I am wondering if DSP can detect signal frequence. for example I have signal 5k or 20K with noise, can DSP distinguish who is who, and apply corresponding filter to it? If it can, how to implement? thanks.
max voltage drop diode 0.2v
I use this diode as a switch, only allow 3.3V go one direction, and when use USB as a power supply, this diode will block the current go to LM2937's out put. so I want this diode has less forward voltage drop. I know Ge diode usally drop 0.2V while Si diode drop...
use of 74ls624
I want to design a frequency generator to produce around between 1000KHz and 1024KHz signal. If I use two crystals, it's a choice. but I want to use VCO to do this. as I have a spare DA on my MCU, I want to use this to adjust VCO to generate Frequcy range 900K ~ 1500Khz. Could...
Re: Why not fit?
I don't think AHDL will help too.
what bothers me is that project 1 use 50 LC(logic cell) and project 2 use 60 LC(logic cell). put them togather then it need 144 LCs.
I already checked the "multi level synthesis for max7000 " before I synthesis.
Thanks your guys.
Why not fit?
Hi, everyone,
I got a new question.
I have tow projects. using EPM7128S. one using 35% resource, another using 59% resource.
so I want to combine them togather. but it failed. can't fit in. seems weird.
If there is anyway to fit them in?
Changing language from verilog to AHDL...
Hi everybody,
I figured it out as per your inspiration.
I use verilog language. when power up the register's value is zero.
This was proved in the target board.
Thanks for you guys help.
wwwrabbit. :D
Thank you for your reply. but I still have questions.
I use Altra EPM128S. how can I define a register variable as a FF with non-inverted output? in verilog language we define a variable like this,
reg abc;
there is no way to tell it is FF with non-inverted output or it is FF with inverted...
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