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I want to realize a time-varying sine signal which amplitude changes linearity with time，expression as vamp=k×t+vamp0.where k is a coefficient and vamp0 is an initial value。
How to realize it inverilog-a？
Thank you in advance^_^
in Federio Bruccoleri doctor degree’s paper
he assumes the MOST only have drain noise （channel noise）
then definitely the drain noise I2n/△f=4KT*r*gm=4KT*NEF*gm
in follow schematic， he calculated the noise factor equal to 1+NEFa+4NEF(AVF-1)/AVF2 at ΔNEF=NEFb-NEFa And...
why the follow circuit diagram which input impedance equal to 1/(gm1a+gm1b) in the radio frequency?
this problem confuse me long time .
thank you for your attention!
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