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Recent content by wufei

  1. W

    Verilog code wont simulate properly

    lack of this line: binaryTo7Seg binaryTo7Seg（,,,）
  2. W

    Does Synopsys LEDA support commands like 'set_false_path'?

    hi downloadman hi shitansh these command lines 'read_verilog read_vhdl analyze' can't compile at all only 'current_design set_false_path' can work but there's nothing happened :( LEDA 2008.06
  3. W

    Does Synopsys LEDA support commands like 'set_false_path'?

    Thank you , downloadman. so I can use set_false_path in a sdc file to disable LEDA checking on an certain path in a RTL design? I have read leda use guide, and SDC checker can only check sdc syntax, differents between two sdc files or svf files. i thought leda dont meet my requirements, am i...
  4. W

    Does Synopsys LEDA support commands like 'set_false_path'?

    there are too many (>6k) warnings with a rule (C_1202) most of these warnings are not useful how can I select the useful ones in the report? that is to say, how can I mute the useless warnings in a simple way? i just want to see certain paths, can set_false_path work?
  5. W

    Modelsim-SE 6.3f no longer displays full Verilog objects?

    modelsimse 6.3f installation no vopt option
  6. W

    Can lint tools check netlist files? (LEDA)

    hi, i am using LEDA these days, Can LEDA do some netlist checks and signal synchronization checks? if yes, how? and where can i get documents about those checks? I thought it can only check RTL codes. thx
  7. W

    What's the difference between '#5 a = b;' and 'a = #5 b;'?

    thanks but it seems that simulations of these two assignments in Modelsim have the same results...
  8. W

    What's the difference between '#5 a = b;' and 'a = #5 b;'?

    difference of 5 how can i verify the difference?
  9. W

    What's the difference between '#5 a = b;' and 'a = #5 b;'?

    #5 a=b What's the difference between '#5 a = b;' and 'a = #5 b;'? #5 a = b; and a = #5 b;
  10. W

    who can share a sample Design Complier synthesis script?

    how to enable multi core design compiler who can share a sample Design Complier synthesis script? not matter what design~ I just want to study synthesis thank you:D
  11. W

    TSMC IC 90nm routing guide

    thank you
  12. W

    About Error Messages on Quartus, Need a hand.

    only 4 control signals may be non-global Error: Cell qrdecom:qrdecom|s04_d1[13] fed by 5 non-global control signals -- only 4 control signals may be non-global Quartus tell me the above error message,but I do not know how to fix it. Its help says: CAUSE: The specified cell is fed by the...
  13. W

    questions about QRD-RLS

    thanks and did u do some topics about QRD-RLS before?
  14. W

    questions about QRD-RLS

    what's this?
  15. W

    questions about QRD-RLS

    请问有谁做过这方面的事情吗？如果你认识中文的话。：）
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