Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by wsong0210

  1. W

    Tools For ASIC/FPGA Verification Engineer

    Do you mean the Verisity Specman tool suite using e language? It is a tool for functional verification. Verisity is bought by Cadence now and Specman is a part of Cadence tools. It is not free. If your University have Cadence support, you can ask for the tool from Cadence through your university.
  2. W

    IC compiler post placement

    yes of course You can do it by manual operations
  3. W

    why input in @always not synthesizable

    although matchen is inside the sensitive list, no signal inside the always block read it. In hardware, it is either positive enable or negative enable. You can make it work by two ways: 1. use matchen as a clock So write as "always @(posedge matchen)" 2. assuming it is a positive enable Add...
  4. W

    Area report: ASIC Design

    Some facts which may help you understand it. 1. The same logic or function can be implemented by different cells, For example, ~(A+B) can be implemented as a 2-input NOR; or 2-input OR plus INV; or 2 INVs plus a 2-input AND. These combinations are the same, but have different cell counts. 2. The...
  5. W

    Intellectual Property blocks .... are 3rd party sources being marginalized?

    you should clarify you are talking about FPGA at the first place. There is actually rarely, if not non-existed, to use a soft-IP in ASIC chip. ASIC designer may have some encrypted codes from IP vendors (foundry or 3rd party), but they are usually for simulation. In other words, IPs in ASIC are...
  6. W

    Process Variations and Timing effects

    As far as I know, the inversion occurs only when the supply voltage is low. In normal case with standard voltage, you should not expect inversion to happen.
  7. W

    Doubts in ASIC frontend flow

    just some add up. 1) Simulation is one way of verification and there are other ways to verify a design, such as LVS, formal verification, etc. 2) Corner case can have many meanings. In functional verification, corner case can be the test cases which is not covered by general test cases. In...
  8. W

    question about report_area command

    gtach is the internal cell lib for DC. DC uses it to elaborate design. This means two points: 1. gtech cells do not have any practical meanings (area, power, delay, etc.) expect for their logic functions. 2. the logic described by gtech is the most complicated one (it is before optimization) To...
  9. W

    [SOLVED] Artisan memory compiler problem

    from the picture, what I can tell is: it is a hierarchy pin and it is the clock. It may be the latency of the clock tree if your timing analyzer can estimate the latency of clock tree at this stage. In synthesis, you can set the clock as ideal; therefore, the clock tree will have zero latency...
  10. W

    Does all the clock buf/inv in the clock tree must have the same rise and fall time?

    In the perfect condition, every single buf has same rise and fall transition time, but different bufs will have different transition times as they have different input transition time and output load. CTS is trying to make the clock tree complying with the timing constraints, which normally have...
  11. W

    How to tolerate the different clock ppm

    I suppose the transceiver is only available for IO. What we are talking is about different clocks inside the design. If you are asking about receiving a signal from another chip, which is driven by another clock, it is totally another question.
  12. W

    Does all the clock buf/inv in the clock tree must have the same rise and fall time?

    each clock buf/inv will have a same rise and fall
  13. W

    Does all the clock buf/inv in the clock tree must have the same rise and fall time?

    Ouch! OK, I am not an expert on analogue but I try to explain. Yes, the transition time of cell depends on input transition time and output load. Assuming the input transition time is Ti and output load is Lo, the transition time of a cell is T(up)=G(up)*Ti(up)*Lo and T(down)=G(down)*Ti(down)*Lo...
  14. W

    How to tolerate the different clock ppm

    there is no way to compensate as clocks from two crystals are from two different sources with two different frequency, even if they claim to have the same frequency. FIFO is useful when a huge amount of data need go across two clock domains. You can also use 2-FF synchronizers to deliver single...
  15. W

    using vhdl & verilog in same project

    I am not sure what you are intent to do. First of all, Verilog/VHDL mixed projects depend heavily on the support of the tools you use. Check the manual of your tools (Quatus) can find out the name convertion between these two languages. The second thing you need to understand, only part of the...
See more

Part and Inventory Search

Back
Top