Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
no, those nets are not clock nets or reset nets. they are the nets in the datapath(mostly between computational logics)
and the FPGA i am using is Cyclone V... it is a pretty slow speed grade fpga. and I am running 300 MHz on it( not too fast i guess )
Hi all,
I am trying to prototype a design into FPGA(Altera). Right now I am having difficulties closing setup timing. critical timing path seem to have very long net routing delay.
The way to fix in ASIC is to break the long net into sections and insert buffers if needed, or simply upsize the...
Hi all,
Can someone give me a list of common DRCs that can see in Layout and the fixes for it ?
quickly coming out of my head,
1. spacing issue( metal to metal, well to well)
2. antenna effect
3. metal density
can someone continue the list here? also can you provide possible solutions...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
