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Hi all,
Most of the material discussing antenna rule says that
metal antenna ratio (AR) is not cumulative (e.g. just count M2 alone, not M2 and M1 together).
But why?
Is this because the gate leakage discharges the metal which is already fabricated?
Maybe for more advanced technology...
I found that the operation works by loading the following lines:
hiSetBindKey("Layout" "<Key>8" "leRotateCB()") ;;rotate
hiSetBindKey("Layout" "<Key>9" "leSetEnv("orientation" "MY")") ;;sideways orientation
hiSetBindKey("Layout" "<Key>0" "leSetEnv("orientation" "MX")")...
Hi guys,
I'm wondering where the via location should be on the power line, considering resistance, current density and fabrication performance.
Take the following picture as an example.
Which one approach do you prefer? Any reason?
Thank you very much for your feedback :grin:
Will
Hi brothers,
I know the function to do rotate by bindkey "leRotateCB()"
How about flip MX and MY by bindkey after clicking move or copy?
I know Key F3 can do the operation, and then click MX/MY buttons
Thanks a lot
Will
NAND Flash systems enable faster write and erase by programming blocks of data
I think this is the reason why NAND flash write speed is higher than NOR flash.
http://umcs.maine.edu/~cmeadow/courses/cos335/Toshiba%20NAND_vs_NOR_Flash_Memory_Technology_Overviewt.pdf
Hi dude,
I'm also a beginner
Do you have .cdsinit file in your home directory?
If no, please create one.
And put the following in this .cdsinit:
load("your_home/your_hotkey_file.il")
Hope this helps ~
Will
apr rtl
Actually, I can do it manually.
But I want to know if there is any automatic way to do so.
The reason for the transform is for the sake of process independent.
After transforming gate-level netlist to RTL netlist, the RTL netlist can then be transformed to any process by synthesis...
rtl netlist
Hello guys ~
I would like to know:
Is there any tools that can transform gate-level verilog netlist TO RTL verilog netlist?
Your guidance is highly appreciated !!
Will
Dear all,
What is the function of tuning fork in flash memory IC layout?
Is it used for positioning the core array?
Is it allowed to place transistors under tuning fork?
Thank you for your sharing in advance.
Will
Provided that Vgs - Vth > 0, a channel is formed from the electrons in substrate which is connected to the ground for NMOS.
When there is potential difference between drain and source, current flows through the transistor.
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