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Recent content by whenyoureachme

  1. W

    Verilog reg declaration @ and gate output

    Thank U Mr. Jack.
  2. W

    Verilog reg declaration @ and gate output

    Hi All, I am very new to VERILOG programming as my first program i have wrote an andgate program in the gate level abstraction with inputs x, y and output z. Here is my first program module andgate (z, x, y); input x, y; output z; wire x, y; reg z; ---------- // I end up with an Syntax Error...
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    [SOLVED] any openings in vlsi pls fwd

    hi friends, i am a fresher looking for a job in VLSI domain, do find any jobs please help me in forwarding to my mail : raghu2882@yahoo.com. thanking u all with regards, Raghu
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