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Re: flash
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Re: IC foundry services?
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pcell means parameterized cell. It can be written in SKILL languge and executing it from CIW window. Or set design environment in Pcell mode and drawing it as layout. And giving the expressions to the corresoponding design. Usually, each device type has a corresponding Pcell layout. So you don't...
For simulation, if you use multipliers in the schematic then the full drain and source area will be given in the netlist. If you use fingers then it should calculate the reduced source/drain area for the simulation.
However, fingering the MOS will give you less parasitic resistance.
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