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Recent content by wesleytaylor

  1. W

    What is the difference between debounce and deglitch in FPGA

    What I've implemented is at https://github.com/w-tr/digital_filters/tree/master/lowpass/rtl From my understanding, #7, wouldn't it be better to have -raw signal -> deglitch -> debounce (basically the otherway round?)
  2. W

    "Hamster Works" disappeared from web - has anybody knows any archive

    Behind the EU restrictive GDPR legislation which is why a lot of companies dont' bother servicing this dying Union. So I can't see this https://www.hamsters.io/ However if you want the guys github try https://github.com/hamsternz He's been active in July2020, so you could ping him a...
  3. W

    What is the difference between debounce and deglitch in FPGA

    All, I'm trying to understand the difference between a deglitch and debounce circuit. I saw something here, but I've never seen a debounce that doesn't reset count on a change...seems like what sh1 was implying is a debounce is a moving average. Maybe someone here can help me with the...
  4. W

    [SOLVED] Unknown operator in P.Ashenden book can someone explain

    Holy smokes, TrickeyDicky you should write a book. I hadn't noticed that he was selectively directing a function, in addition to the types. I'm so used to seeing an infix function used as a (func) b, that I completely forgot the written implementation is "func" (a : type, b : type). However...
  5. W

    [SOLVED] Unknown operator in P.Ashenden book can someone explain

    Hello, Background - After 10 years in the business I was writing my own collaborations of VHDL rules/ best practices etc. I decided to review one of the books on my shelf, "The student Guide to VHDL" by Peter J. Ashenden. Chapter 7.1 Package Declarations, Figure 7-1 and Figure 7.2 package...
  6. W

    Xilinx synthesis directives within a VHDL 2008 package definition

    Well in my design. IT works for synthesis. However I didn't use xsim for simulation because it couldn't handle vhdl2008. Examples of if rst then killed the xsim. It just cannot handle inferred (??) operator. Therefore I'm not surprised if it cannot handle pragma commands. Give RTL_SYNTHESIS...
  7. W

    Xilinx synthesis directives within a VHDL 2008 package definition

    Dpaul, try the following constant sim_byte_endian : boolean := false -- pragma synthesis_off or true -- pragma synthesis_on...
  8. W

    [SOLVED] Need help creating Vivado Timing Constraint

    What I've discovered - Easiest solution to overcome my problem on a Xilinx device is to instantiate a xpm block - xpm_cdc_single/xpm_cdc_array_single. However when trying to be clever/unnecessarily complex. I've looked at a_scoped_xdc file and dynamic_period constraint Such that...
  9. W

    [SOLVED] Need help creating Vivado Timing Constraint

    Hello all, Situation is a follows. Design in Vivado 2018.4 Have multiple signals going from clock domain A to clock domain B. I have created a synchronising FF to handle these signals. Furthermore I've created an entity that structurally instantiates the collection of sync'ing FF required to...
  10. W

    [SOLVED] VHDL scope vs visibility vs visibility by selection

    Thanks Tricky, I was aware that the ^ - equivalent to "cd .." - looks up a level. However I'm surprised to see that the order of block declarations matter. Although the statements declared within the architecture are concurrent to each other, it appears that the order matters. I don't know...
  11. W

    [SOLVED] VHDL scope vs visibility vs visibility by selection

    Hello all, This following is a derived from my desire to keep a signal declaration local to a specific block, but use it in a different block. I know if I was to move the "scope" of the signal declaration to the architecture I would be able to apply visibility by selection. Can a signal local...
  12. W

    Inferred VHDL dual port RAM template

    process(clk) is begin if rising_edge(clk) then prev_read_addr <= read_addr; end if; end process; process(clk) is begin if rising_edge(clk) then if prev_read_addr /= read_addr then r_valid_slv(0) <= '1'; elsif we='1' then r_valid_slv(0) <= '1'; else r_valid_slv(0) <= '0'...
  13. W

    Inferred VHDL dual port RAM template

    How important is portability vs vendor ip instantiation? Just a brain dump - Based on the code presented you'll always have to wait 1 cycle after we='1' before your see write value pushed out onto the read q signal. Why not assign a valid signal associated with your read that is either delayed...
  14. W

    HELP ME the newbie with Verilog Code

    I want to help, but this is blatant offloading of work. How are you going to get any better? You need to know the following 1. You use the clock to generate a counter. 2. Based on clock speed a certain multiple will give you a second. 3. You can represent events that tick over to implement...
  15. W

    Shifting control from one module to another iteratively

    Step 1, create a vector-array of your data Step 2, Use generate statements to iteratively connect the previous. type x is array<> of std_logic_vector(<>) signal data_in : x ... -- note this is pseudo code. ... G_label : for I in array_range generate --loop begin uut : component...

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