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Recent content by weny0247

  1. W

    Hot Topic of Analog IC research?

    I think Hign Speed Interface !and !SOC
  2. W

    How to design a CMOS pll?

    pll is very diffcult to design !
  3. W

    Where can download TSMC design kit for ADS ? Thx

    tsmc design kit tsmc design kit ads good things
  4. W

    What is POR and LVD in a chip ?

    POR and LVD POwer on reset
  5. W

    Hot Topic of Analog IC research?

    PLL/DLL A/D
  6. W

    icfb and icms difference

    icfb icmb what difference betwen icms and icfb in Cadence??which is better???
  7. W

    how can i covert 5v to 2.5v ?

    Thank solartorch ! you ways is good!
  8. W

    how can i covert 5v to 2.5v ?

    I can not use inductance !so I can not use buck! only sue LDO
  9. W

    what EDA tools simulate full-digital delay phas-locked loop

    I see! Thank vijay_nag
  10. W

    need help LDO 60mA Load 5v-2.5v

    Thanks Cinch and Ianp! I Have select LDO! througn simulation! I have implent its purpose! my english is poor!plese forgive me!!hehe
  11. W

    how can i covert 5v to 2.5v ?

    Thangks you all! ic supply is 5v !but ic working voltage is 2.5v ! ic current is 50-100mA,!what i think is choose dc-dc or ldo! if iselect dc-dc !I dont hope to use L or lager C !
  12. W

    need help LDO 60mA Load 5v-2.5v

    Now I need to design LDO ,about 100mA Load, From 5v to 2.5v !Please give some advise !Thanks!
  13. W

    how can i covert 5v to 2.5v ?

    I need covert 5v to 3v !how many way to implent it!?help me !thangks
  14. W

    How I SImulate fullly digital delay phase-locked loop!

    Now I am design A addll！I need help for how i simulate ! thanks!
  15. W

    what EDA tools simulate full-digital delay phas-locked loop

    thanks !Can you tell me how I simulation PFD ?Thanks.
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