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It is possible. Actually when you design a PA, you have to do such an impedance matching for maximum output power. You can try several segments of L-C to realize it.
smith chart short circuit
I guess that you are building a matching network and also harmonic traps at the same time. At harmonic frequency it is close to short. I noticed that you are using magnitute of reflection. I think a better choice is S21 in dB. And another suggestion is that -30dB and...
For TRL calibration, you can build different delay lines for different bands. It will be ok if you control the phase delay in the certain range, e.g. 30~150 deg. So TRL is not a narrow band technique.
TRL can be more accurate than SLOT, especially for high frequency. And the most important, it...
- probing test suggested
- VNA to get S-parameter
- calibration is a Must
- deembeding is a Must
Hope it help. I think there are some docs you can find by Google.
Hi
I agree that it is better to firstly make sure if your BJT can be lacated in DNW. In some technology, e.g. IBM SiGe, it is real that BJT is in DNW. Actually DWN is used to form an isolated p-type substrate.
If it is sure that your structure is right, i suggest to check the LVS script. It...
ADS is stronger in RF domain. It is one of the best tools of RF system and board designers. You can also use it to design chip level circuits and layout. As mentioned above, the layout tool is not so interface friendly. When dealing with large scale transistor level netlist, some time there is...
Re: Device Characterization
Hi diemilio,
I think it is not an easy job. However, it is an good experience to do something on modeling. If I were given the chance, I'd like to try.
I just want to suggest some documents on ICCAP. You can easily get them on Agilent's website or via Google.
It depends on your technology. For example, it might be used to define Normal VT, Low VT or Zero VT transistors. So some extra masks are needed and they will also be needed when stream out.
I think you can get Gm from its definition d(i)/d(V).
Another method is to check the detailed operation point simulation summary, Gm will be listed in it for each transistor.
Just a suggestion.
Since multiple power domain is used, VDD1, VDD2 and VDD3, maybe the ESD protection between those different VDDs should be considered, except the Vss issue.
I think it is normal. If you read some commercial PA data sheet, you can find some specs are defined under certain output VSWR, e.g. 12:1. That is, output is not matched.
Current has two parts, through the transistor and through the load. When load is changing, Icc is changing (not Icq, if you...
"8 metal layers, between every two metal layers, there are 4 dielectric layers" , looks like TSMC 0.13um RFCMOS. I did not work on such a complex substrate. However, I know some friends used this technology a few years ago and they met a similar problem. At that time their solution is to use...
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