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glitch in current steering dac
the circuit cell
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I'm design a DAC used the classic current steering circuit. But I need a large fixed output voltage range.
It cause large step in the common source node of switch M3 and M4 (>300mv), also a...
I'm reading the paper "A Rail-to-Rail Constant-gm Low-Voltage CMOS
Operational Transconductance Amplifier" Ferri, JSSC. I'm puzzled with the explaination of the circuit Fig.2(b), especially the voltage regulating. Could someone give me a clear explaination?
I think it's hard to implement reference current in intergrated circuit because the resister.
In razavi's book he instead resister with switched capacitor. I think you could try it ,but the clock and speed maybe some difficuit.
Thanks, i saw Razavi's book "design analog cmos IC', in figure 3.51,he said when m1 is cut off, the voltage of node "x" was 'vb-vth2'. But i think it is floating, so i am puzzled
i'm puzzled with a simple question.
For a simple mosfet,when Vg and Vd is fixed, Id=0, and Vs is floating. How much is the Vgs, Vth or 0, or we can't get it?
i'm reading allen's "cmos analog circuit design"
in example 10.4.2,i think the answer should will be (25/16)Vref, but it comes (19/16)Vref, i think the way he give us is right.
Could someone give me the reason?
Is there another coding way? 11001 is not 25?
i use a simple differental pair with res load as a limiting output stage in a front-end amplifier.
but when i give a differental singal in,the output achieve the limiting state but with a large peak. could someone give me some advise? i use a resistance as the emitter degeneration.
cherryhooper help
actually i could get b/w and gain in one stage,also i could get a 30db 10gb with 2 stage,but i find it's hard to get a flat amplitude response. so the eyedigram is so bad.
have you met this question?
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