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Recent content by wallacebooth

  1. W

    How to constraint Reset signal in chip level?

    Thanks for all of you
  2. W

    How to constraint Reset signal in chip level?

    Thanks a lot, but these violation too large, is it diffcult to fix during the back-end??
  3. W

    How to constraint Reset signal in chip level?

    Hi, all: in my design, I use two stage Flip-flop to synchronize asynchronous Reset signal, when synthesis using Synopsys DC, there are Removal violation in FF1 and FF2, any body who can tell me how can i add constraint to fix these violation? Thanks a lot! DC rpt: Startpoint...
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