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I am designing a 10bit pipeline ADC. The schematic simulation shows that the odd harmonics are too large(especially,the third harmonic is 55dB).
Can anybody give me some suggestion on how to find the reason?
Thanks.
Hi all
I am desing a SC SHA. Can anybody tell me how to find the input refer noise with simulation tools like hspice or spectre? I want to know how to select the value of sample capacitor.
BRS
Wai
mirror-protected level shifter
I am designing a high speed level shift used in PLL's PFD output.
And I find a circuit called Mirror-Protected Level Shifter(see att.)
Can anybody tell me the theory about it?
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