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Hello Forum,
I am working on gate level simulations for generating saif file for power estimation. I am running simulations on post ICC generated netlist and sdf file(generated from prime time using spef file extracted using star rc tool). In sdf file the min::max delays corresponds to the...
You can either do back pressure to all the pipeline stages, or instead send a signal from the fifo to the source(suppose say ab) of first pipeline stage saying not to send the data. From that source ab there will be a signal going to it's source not send any data. The reason I suggested...
Suppose say you have 6 pipeline stages and a fifo after that. When the write pointer in the fifo points to FIFO_DEPTH-6-1, you can send a signal to the source of the data to the first pipeline stage saying not to send data anymore.
Hello ThisIsNotSam,
I synthesized the design at 600Mhz for 28nm technology and 400Mhz for 40nm technology. My testbench runs at 100Mhz. I am not using the SDF files. Instead I am using unit delays specified in the standard cells verilog file. The goal is to generate saif files for respective...
Hello Forum,
I did post synthesis simulation on netlist generated for two different technology nodes(28nm & 40nm) for the same design. The post synthesis netlist simulation worked for 28nm technology node, but it didn't work for 40nm node. The design met timing in both technology nodes. I...
Hello Forum,
I work on front end synthesis of the design using design compiler topographical. After synthesis, there are no timing violations. But I am seeing "max_transition" violation. Is it something which we resolve at front end or at back end?
You need to run post synthesis simulation on the synthesized netlist and generate saif file first. Later load the synthesized design and libraries and give generated saif file as an input to design compiler again and run the design. You will generate the power report.
Hello Forum,
I am working on RTL synthesis of an ECC Decoder(which has many sub modules) using design compiler, and I encountered a timing violation and the critical path is in sub module ABC. Accidentally I turned on a pipeline stage in different path (critical path and this path are not...
Hello forum,
I am investigating on code coverage. I have a design and upon doing coverage analysis, the coverage report shows that my test bench does 70% of code coverage. Is it necessary to have 100% code coverage? If a fsm has 4 states aa-bb-cc-dd and suppose aa-cc transition should never...
Hi all,
I am designing a decoder and my design uses memory. For some of the memory blocks I am using compiled memories and for other memory blocks I am synthesizing it as flipflops(synthesizing as flipflops increasing area). I am thinking of synthesizing the memory as latches.
Is it ok to...
Hi Forum,
I ran a synthesis using design compiler for a using standard cell library which has operating conditions(Voltage=1.05V, Temp=25C). Now I want to run synthesis for different operating conditions (voltage=1.05V, temp=25C). I used DC command set_operating_conditions to set the operating...
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