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The foundry guidlines for ir signoff is:
static ir drop : 3%
dynamic ir drop : 12%
I wonder what's the timing scale for dynamic ir drop? us, ns or ps?
Dose it affect sta timing?
I wonder the principle of power switch. Is it a transistor? If so, there should be Drain-Source voltage drop. This would derate VDD to he block that they switch off, and have bad effect on timing and power dissipation.
There are on die power gating cells, connect to VDD or VSS. How about their voltage drop? How dose they affect the circuit timing closure? Can anyone give me some clue?
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