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Recent content by vlsimember

  1. V

    Align of data stream from asynchronous clock domains where clock frequencies are same

    FvM Both the data stream ate coming separately. How can the alignment be done using FIFOs and how? How many FIFOS are needed? Should the FIFOs be asynchronous or synchronous FIFO? Can please explain the architecture with reasons?
  2. V

    RTL work in a test chip

    Anilineda Do you work in testchip division? Which country do you work in? May I know which company fo you work in? Is the experience gain by a RTL Designer working in a test chip team is less, equal or more valuable than the experience gained by a RTL Designer working in a RTL Design team for...
  3. V

    Align of data stream from asynchronous clock domains where clock frequencies are same

    Suppose a serial data coming from one clock domain CLK1. Another serial data is coming from another clock domain CLK2. Both CLK1 and CLK2 are of same frequency but they are asynchronous to each other. How to allign both the data streams?
  4. V

    RTL work in a test chip

    How does a test chip team require RTL designers? What do the RTL designers do in a test chip team? Please elaborate. How does the work of a SOC RTL designer differs from the work of a RTL designer for test chip? I saw one post in edaboard by mr_vasanth on test chip. But I am looking for some...
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